Quan Pan - RankMe

72 papers C 3Journal 29Unranked 40

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	8.9 A 72Gb/s/pin Single-Ended Simultaneous Bi-Directional Transceiver with C-Peaking Leakage Cancellation and Dual-Loop Hybrid Impedance Calibration for Chiplet Interfaces. ISSCC Xuxu Cheng, Hongzhi Wu, Zhenghao Li, Weitao Wu, Xiongshi Luo, Yangyi Zhang, Quan Pan
2026	J	`jnl`	A 128-Gb/s PAM-4 Transmitter With Edge-Boosting Pulse Generator and Pre-Emphasis Asymmetric Fractional-Spaced FFE in 28-nm CMOS. IEEE J. Solid State Circuits Hongzhi Wu, Xuxu Cheng, Weitao Wu, Liping Zhong, Catherine Wang, Yangyi Zhang, Xiongshi Luo, Dongfan Xu, Quan Pan
2026	J	`jnl`	A 2 × 80 Gb/s Single-Ended TAS-TIS PAM-4 Receiver Front-End With Crosstalk Cancellation and Signal Reutilization in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Yangyi Zhang, Liping Zhong, Taiyang Fan, Xiongshi Luo, Hongzhi Wu, Xuxu Cheng, Weitao Wu, Wentao Zhou, Dongfan Xu, Quan Pan
2026	J	`jnl`	A 48-Gb/s Inductorless PAM-4 Optical Receiver With 1.28-pJ/bit Efficiency in 28-nm CMOS. IEEE J. Solid State Circuits Chongyun Zhang, Li Wang, Fuzhan Chen, Quan Pan, Xianbo Li, C. Patrick Yue
2026	J	`jnl`	A 50 Gb/s PAM-4 Receiver Featuring Current-Reuse AFE and Single-Loop Half-Rate Reference-Less Bang-Bang CDR in 40-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Zhenghao Li, Wentao Zhou, Wenbo Xiao, Xiongshi Luo, Quan Pan
2026	—	`conf`	A 72Gb/s/pin Single-Ended Driver-Cooperative Coded PAM3 Transceiver with Asymmetric Data-Dependent Equalization and Bias-Peaking for Chiplets and Memory Interfaces. ISSCC Hongzhi Wu, Xuxu Cheng, Yangyi Zhang, Xiongshi Luo, Zhenghao Li, Weitao Wu, Quan Pan
2025	—	`conf`	36.6 A 112Gb/s 0.61pJ/b PAM-4 Linear TIA Supporting Extended PD-TIA Reach in 28nm CMOS. ISSCC Yangyi Zhang, Zhenyu Yao, Wentao Zhou, Xiongshi Luo, Zhenghao Li, Dongshen Zhan, Quan Pan
2025	—	`conf`	A 0.3-to-10.1 GHz 33.8fSRMS-Jitter Hybrid Injection-Locked Eight-Phase Clock Generator with Adaptive Mismatch Cancellation Technique for High-Speed Links in 28nm CMOS. CICC Hongzhi Wu, Xuxu Cheng, Liping Zhong, Yangyi Zhang, Weitao Wu, Xiongshi Luo, Quan Pan
2025	—	`conf`	A 100Gbaud 4Vppd Distributed Linear Driver with Cross-Folded Transmission Lines and Cross-Coupled Gm Cells for Built-in 5-Tap FFE in 0.13µm SiGe BiCMOS. ISSCC Fuzhan Chen, C. Patrick Yue, Quan Pan
2025	J	`jnl`	A 112-Gb/s Single-Ended PAM-4 Transceiver Front-End for Reach Extension in Long-Reach Link. IEEE Trans. Circuits Syst. I Regul. Pap. Xiongshi Luo, Xuewei You, Jiahan Fu, Zhenghao Li, Liping Zhong, Mengjie Song, Taiyang Fan, Wenbo Xiao, Hongzhi Wu, Yangyi Zhang, Chenchang Zhan, Quan Pan
2025	J	`jnl`	A 2 × 112 Gb/s/pin Single-Ended Crosstalk Cancellation Transceiver With 31-dB Loss Compensation in 28-nm CMOS. IEEE J. Solid State Circuits Liping Zhong, Hongzhi Wu, Yangyi Zhang, Xuxu Cheng, Weitao Wu, Catherine Wang, Xiongshi Luo, Taiyang Fan, Dongfan Xu, Zhenghao Li, Quan Pan
2025	J	`jnl`	A 2 × 24 Gb/s Single-Ended Transceiver With Channel-Independent Encoder-Based Crosstalk Cancellation in 28-nm CMOS. IEEE J. Solid State Circuits Hongzhi Wu, Liping Zhong, Weitao Wu, Catherine Wang, Xuxu Cheng, Xiongshi Luo, Yangyi Zhang, Dongfan Xu, Quan Pan
2025	J	`jnl`	A 56-Gb/s PAM-4 VCSEL Transmitter With Piecewise Compensation Scheme in 40-nm CMOS. IEEE J. Solid State Circuits Fuzhan Chen, Chongyun Zhang, Li Wang, Quan Pan, C. Patrick Yue
2025	J	`jnl`	A 64 Gb/s/pin Single-Ended PAM-4 Transmitter With a Merged Preemphasis Capacitive-Peaking Crosstalk Cancellation Scheme for Memory Interfaces in 28-nm CMOS. IEEE J. Solid State Circuits Weitao Wu, Hongzhi Wu, Liping Zhong, Xuxu Cheng, Xiongshi Luo, Dongfan Xu, Catherine Wang, Zhenghao Li, Quan Pan
2025	—	`conf`	Analysis and Classification of Modulated Eye Diagram Signals Using Convolutional Neural Networks Model Toward an Intelligent Optical Communication System. ICCBN Yue Geng, Xuhui Liu, Chun-Zhang Chen, Liang Wang, Quan Pan, Hanming Wu
2025	J	`jnl`	Design and Analysis of a Type-II Sampling PLL With Automatic Frequency and Phase Calibrations Achieving 0.62-μs Locking Time. IEEE Trans. Circuits Syst. I Regul. Pap. Jian Yang, Tailong Xu, Xi Meng, Zhenghao Li, Jun Yin, Rui Paulo Martins, Pui-In Mak, Quan Pan
2024	—	`conf`	13.5 A 64Gb/s/pin PAM4 Single-Ended Transmitter with a Merged Pre-Emphasis Capacitive-Peaking Crosstalk-Cancellation Scheme for Memory Interfaces in 28nm CMOS. ISSCC Weitao Wu, Hongzhi Wu, Liping Zhong, Xuxu Cheng, Xiongshi Luo, Dongfan Xu, Catherine Wang, Zhenghao Li, Quan Pan
2024	—	`conf`	7.5 A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE. ISSCC Xiongshi Luo, Xuewei You, Zhenghao Li, Hamed Mosalam, Dongfan Xu, Taiyang Fan, Hongchang Qiao, Wentao Zhou, Hongzhi Wu, Liping Zhong, Patrick Yin Chiang, Quan Pan
2024	—	`conf`	7.6 A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS. ISSCC Liping Zhong, Hongzhi Wu, Yangyi Zhang, Xuxu Cheng, Weitao Wu, Catherine Wang, Xiongshi Luo, Taiyang Fan, Dongfan Xu, Quan Pan
2024	—	`conf`	A 128Gb/s PAM-4 Transmitter with Edge-Boosting Pulse Generator and Pre-Emphasis Asymmetric Fractional-Spaced FFE in 28nm CMOS. CICC Hongzhi Wu, Weitao Wu, Liping Zhong, Xuxu Cheng, Yangyi Zhang, Xiongshi Luo, Dongfan Xu, Xindan Yu, Quan Pan
2024	—	`conf`	A 2x112 Gb/s 0.34 pJ/b/Lane Single-Ended PAM4 Receiver with Multi-Order Crosstalk Cancellation and Signal Reutilization Technique in 28-nm CMOS. VLSI Technology and Circuits Liping Zhong, Yangyi Zhang, Xiongshi Luo, Hongzhi Wu, Xuxu Cheng, Weitao Wu, Zhenghao Li, Quan Pan
2024	J	`jnl`	A 2×56 Gb/s 0.78-pJ/b PAM-4 Crosstalk Cancellation Receiver With Active Crosstalk Extraction Technique in 28-nm CMOS. IEEE J. Solid State Circuits Liping Zhong, Hongzhi Wu, Weitao Wu, Catherine Wang, Wenbo Xiao, Xiongshi Luo, Yangyi Zhang, Dongfan Xu, Wei Wang, Taiyang Fan, Zhenghao Li, Xuxu Cheng, Quan Pan
2024	—	`conf`	A 2×56Gb/s Single-Ended Orthogonal PAM-7 Transceiver with Encoder-Based Channel-Independent Crosstalk Cancellation in 28-nm CMOS. VLSI Technology and Circuits Xuxu Cheng, Hongzhi Wu, Liping Zhong, Weitao Wu, Quan Pan
2024	—	`conf`	A 48-Gb/s Half-Rate PAM4 Optical Receiver with 0.27-pJ/bit TIA Efficiency, 1.28-pJ/bit RX Efficiency, and 0.06-mm VLSI Technology and Circuits Chongyun Zhang, Li Wang, Zilu Liu, Fuzhan Chen, Quan Pan, Xianbo Li, C. Patrick Yue
2024	—	`conf`	A 56-Gbaud 7.3-Vppd Linear Modulator Transmitter with AMUX-Based Reconfigurable FFE and Dynamic Triple-Stacked Driver in 130-nm SiGe BiCMOS. CICC Fuzhan Chen, C. Patrick Yue, Quan Pan
2024	—	`conf`	A 6.0-to-6.9GHz 99fsrms-Jitter Type-II Sampling PLL with Automatic Frequency and Phase Calibration Method Achieving 0.62μs Locking Time in 28nm CMOS. CICC Jian Yang, Tailong Xu, Xi Meng, Zhenghao Li, Jun Yin, Pui-In Mak, Rui Paulo Martins, Quan Pan
2024	—	`conf`	A High Linearity Driver with a Wide Common-Mode Voltage Range in 130-nm BiCMOS. ICTA Jiayao Li, Jian Yang, Taiyang Fan, Kun Zhang, Junhua Zhu, Quan Pan
2024	J	`jnl`	Signal Integrity Augmentation Techniques for the Design of 64-GBaud Coherent Transimpedance Amplifier in 90-nm SiGe BiCMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Shuaizhe Ma, Nianquan Ran, Xi Liu, Yifei Xia, Songqin Xu, Wei Huang, Chen Tan, Jing Li, Zhenyu Yin, Shaoheng Lin, Jianhua Pan, Zhe Chen, Chaoxuan Zhang, Wu Wen, Quan Pan, Zhongming Xue, Xiaoyan Gui, Li Geng, Dan Li
2023	J	`jnl`	A 0.96-0.9-V Fully Integrated FVF LDO With Two-Stage Cross-Coupled Error Amplifier. IEEE Trans. Circuits Syst. II Express Briefs Dongfan Xu, Yangyi Zhang, Xiongshi Luo, Zhenghao Li, Quan Pan
2023	—	`conf`	A 2 x 24Gb/s Single-Ended Transceiver with Channel-Independent Encoder-Based Crosstalk Cancellation in 28nm CMOS. A-SSCC Hongzhi Wu, Weitao Wu, Liping Zhong, Xuxu Cheng, Xiongshi Luo, Zhenghao Li, Dongfan Xu, Quan Pan
2023	—	`conf`	A 2.05-pJ/b 56-Gb/s PAM-4 VCSEL Transmitter with Piecewise Nonlinearity Compensation and Asymmetric Equalization in 40-nm CMOS. ESSCIRC Fuzhan Chen, Chongyun Zhang, Li Wang, Quan Pan, C. Patrick Yue
2023	—	`conf`	A 28-Gb/s PAM-4 Fully-Integrated Optical Receiver with High-Speed Silicon Photodetector in 28-nm CMOS. ICTA Dongshen Zhan, Liping Zhong, Wentao Zhou, Zhenyu Yao, Xiongshi Luo, Yangyi Zhang, Hemiao Wang, De Zhou, Quan Pan
2023	J	`jnl`	A CMOS slew-rate controlled output driver with low process, voltage and temperature variations using a dual-path signal-superposition technique. IET Circuits Devices Syst. Xiaoyan Gui, Renjie Tang, Kai Li, Kanan Wang, Dan Li, Quan Pan, Li Geng
2023	C	`conf`	A Fully-Integrated LDO with Two-Stage Cross-Coupled Error Amplifier for High-Speed Communications in 28-nm CMOS. ISCAS Dongfan Xu, Yangyi Zhang, Zhenghao Li, Xiongshi Luo, Pingyi Cai, Hongzhi Wu, Liping Zhong, Weitao Wu, Liru Zhu, Quan Pan
2023	—	`conf`	A Power-Efficient $\boldsymbol{4}-\mathbf{V}_{\mathbf{ppd}}$ 128-Gb/s PAM-4 Optical Modulator Driver with Merged BV Doubler Topology in 130-nm BiCMOS. ICTA Shuo Feng, Fuzhan Chen, Quan Pan
2022	—	`conf`	A 112-Gb/s Single-Ended PAM-4 Transceiver Front-End for Reach Extension in Long-Reach Link. ESSCIRC Xiongshi Luo, Xuewei You, Jiahan Fu, Zhenghao Li, Liping Zhong, Taiyang Fan, Zhang Qiu, Wenbo Xiao, Yong Chen, Quan Pan
2022	—	`conf`	A 160-Gb/s 0.37-pJ/bit PAM4 Optical Receiver in 28-nm CMOS. APCCAS Leiming Wang, Xiongshi Luo, Dongfan Xu, Zhang Qiu, Yiyang Yan, Quan Pan
2022	—	`conf`	A 200-Gb/s PAM-4 Feedforward Linear Equalizer with Multiple-Peaking and Fixed Maximum Peaking Frequencies in 130nm SiGe BiCMOS. ICTA Zhengzhe Jia, Taiyang Fan, Dongfan Xu, Dongshen Zhan, Linxuan Hu, Zhengyang Zhang, Yanchao Wang, Chun-Zhang Chen, Xuhui Liu, Hanming Wu, Quan Pan
2022	—	`conf`	A 2×50Gb/s Single-Ended MIMO PAM-4 Crosstalk Cancellation and Signal Reutilization Receiver in 28 nm CMOS. ESSCIRC Liping Zhong, Hongzhi Wu, Weitao Wu, Wenbo Xiao, Xiongshi Luo, Dongfan Xu, Xuxu Cheng, Zhenghao Li, Taiyang Fan, Quan Pan
2022	—	`conf`	A 4-Vppd160-Gb/s PAM-4 Optical Modulator Driver with All-Pass Filter-Based Dynamic Bias and 2- Tap FFE in 130-nm BiCMOS. APCCAS Shuo Feng, Fuzhan Chen, Zhenghao Li, Wentao Zhou, Dongfan Xu, Chun-Zhang Chen, Xuhui Liu, Hanming Wu, Quan Pan
2022	J	`jnl`	A 54-68 GHz Power Amplifier With Improved Linearity and Efficiency in 40 nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Hamed Mosalam, Wenbo Xiao, Xiaoyan Gui, Dan Li, Quan Pan
2022	J	`jnl`	A 6.15-10.9 Gb/s 0.58 pJ/Bit Reference-Less Half-Rate Clock and Data Recovery With "Phase Reset" Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. Wenbo Xiao, Qiwei Huang, Hamed Mosalam, Chenchang Zhan, Zhiqun Li, Quan Pan
2022	J	`jnl`	Analysis and Design of Tuning-Less mm-Wave Injection-Locked Frequency Dividers With Wide Locking Range Using 8th-Order Transformer-Based Resonator in 40 nm CMOS. IEEE J. Solid State Circuits Qiyao Jiang, Quan Pan
2021	—	`conf`	8.5 A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm. ISSCC Danfeng Xu, Yu Kou, Paul Lai, Zichuan Cheng, Tze Yin Cheung, Larry Moser, Yang Zhang, Xiaolong Liu, Man Pio Lam, Haikun Jia, Quan Pan, Wing Hong Szeto, Chi Fai Tang, Ka Fai Mak, Khawar Sarfraz, Tairan Zhu, Ming Kwan, Emily Yim Lee Au, Cormac Conroy, Kai-Keung Chan
2021	—	`conf`	A 100GBaud Optical Receiver Front-End in 90nm SiGe BiCMOS. ICTA Chuanhao Yu, Zhenyu Yin, Chenfan Cao, Shiti Huang, Quan Pan, Xiaoyan Gui, Li Geng, Dan Li
2021	J	`jnl`	A 19-48.3-GHz 6 IEEE Trans. Circuits Syst. II Express Briefs Junhua Zhu, Qiyao Jiang, Hamed Mosalam, Chenchang Zhan, Quan Pan
2021	J	`jnl`	A 4 × 10 Gb/s Adaptive Optical Receiver Utilizing Current-Reuse and Crosstalk-Remove. IEEE Trans. Very Large Scale Integr. Syst. Juncheng Wang, Xuefeng Chen, Rui Bai, Patrick Yin Chiang, Quan Pan
2021	J	`jnl`	A 56-Gb/s PAM4 Receiver Analog Front-End With Fixed Peaking Frequency and Bandwidth in 40-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Zhenghao Li, Minzhe Tang, Taiyang Fan, Quan Pan
2021	J	`jnl`	A 57-100 GHz 0.13 μm SiGe power amplifier with high output power and efficiency. Microelectron. J. Hamed Mosalam, Quan Pan
2021	—	`conf`	A 720-mVpp 224-Gb/s PAM4 Optical Receiver with Multiple Peaking Techniques in 130-nm SiGe BiCMOS. APCCAS Qi Zhang, Xiongshi Luo, Zhenghao Li, Dongfan Xu, Siqiang Zhu, Leiming Wang, Zhenjiang Mao, Xiaoyan Gui, Dan Li, Hongyu Yu, Quan Pan
2021	C	`conf`	An Area-Efficient Low Quiescent Current Output Capacitor-Less LDO with Fast Transient Response. ISCAS Hongchang Qiao, Chenchang Zhan, Quan Pan, Yutian Chen, Ning Zhang
2021	—	`conf`	Design and Co-Simulation of QPSK and NRZ/PAM-4/PAM-8 VCSEL-Based Optical Links Utilizing an Integrated System Evaluation Engine. ASICON Fuzhan Chen, Chongyun Zhang, Tianxin Min, Bo Xu, Quan Pan, C. Patrick Yue
2020	J	`jnl`	A -40 °C to 120 °C, 169 ppm/°C Nano-Ampere CMOS Current Reference. IEEE Trans. Circuits Syst. II Express Briefs Qiwei Huang, Chenchang Zhan, Lidan Wang, Zhiqun Li, Quan Pan
2020	C	`conf`	A 112-Gb/s PAM-4 Linear Optical Receiver in 130-nm SiGe BiCMOS. ISCAS Dan Li, Shengwei Gao, Yongjun Shi, Xiaoyan Gui, Nan Qi, Zhiyong Li, Quan Pan, Patrick Chiang, Li Geng
2020	J	`jnl`	A 15-Gb/s 0.0037-mm² 0.019-pJ/Bit Full-Rate Programmable Multi-Pattern Pseudo-Random Binary Sequence Generator. IEEE Trans. Circuits Syst. II Express Briefs Junfeng Hu, Zhao Zhang, Quan Pan
2020	—	`conf`	A 224-Gb/s PAM4 High-Linearity, Energy-Efficiency Differential to Single-Ended Driver in 130-nm SiGe BiCMOS. ICTA Jiahan Fu, Pingyi Cai, Xiongshi Luo, Xuewei You, Liping Zhong, Wenbo Xiao, Fujiang Lin, Yao Li, Quan Pan
2020	J	`jnl`	A 42-dB Ω 25-Gb/s CMOS Transimpedance Amplifier With Multiple-Peaking Scheme for Optical Communications. IEEE Trans. Circuits Syst. II Express Briefs Quan Pan, Yipeng Wang, C. Patrick Yue
2020	J	`jnl`	A Low-Power PAM4 Receiver With an Adaptive Variable-Gain Rectifier-Based Decoder. IEEE Trans. Very Large Scale Integr. Syst. Quan Pan, Li Wang, Xiongshi Luo, C. Patrick Yue
2020	—	`conf`	Fully-Differential 100-Gb/s PAM4 Cross-Coupled Regulated Transimpedance Amplifier. ICTA Dongfan Xu, Zhang Qiu, Xiongshi Luo, Xuewei You, Wenbo Xiao, Siqiang Zhu, Minzhe Tang, Zhenghao Li, Quan Pan
2020	—	`conf`	PAM-X™: A 25Gb/s-PAM4 Optical Transceiver Chipset for 5G Optical Front-Haul. OFC Xin Wang, Yi Peng, Yuanxi Zhang, Tao Xia, Yifan Wu, Juncheng Wang, Lei Wang, Liujia Song, Lei Zhao, Shenglong Zhuo, Quan Pan, Xuefeng Chen, Patrick Yin Chiang, Rui Bai
2019	—	`conf`	A 50Gb/s PAM-4 Retimer-CDR + VCSEL Driver with Asymmetric Pulsed Pre-Emphasis Integrated into a Single CMOS Die. OFC Shang Hu, Tingyu Yao, Bozhi Yin, Chunyu Song, Lei Zhao, Juncheng Wang, Lei Wang, Rui Bai, Xin Wang, Tao Xia, Yi Peng, Binbin Yao, Yuan Li, Xuefeng Chen, Quan Pan, Nan Qi, Patrick Yin Chiang
2019	J	`jnl`	A Fully Integrated 25 Gb/s Low-Noise TIA+CDR Optical Receiver Designed in 40-nm-CMOS. IEEE Trans. Circuits Syst. II Express Briefs Juncheng Wang, Quan Pan, Yajie Qin, Xuefeng Chen, Shang Hu, Rui Bai, Xin Wang, Yaxin Cai, Tao Xia, Yuanxi Zhang, Jianxu Ma, Nan Qi, Patrick Yin Chiang
2019	—	`conf`	Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique. APCCAS Lingshan Kong, Yong Chen, Haohong Yu, Quan Pan, Chirn Chye Boon, Pui-In Mak, Rui Paulo Martins
2017	J	`jnl`	A 60-GHz 4-Gb/s Fully Integrated NRZ-to-QPSK Fiber-Wireless Modulator. IEEE Trans. Circuits Syst. I Regul. Pap. Yipeng Wang, Duona Luo, Quan Pan, Liwen Jing, Zhixin Li, C. Patrick Yue
2017	—	`conf`	A low-power PAM4 receiver using 1/4-rate sampling decoder with adaptive variable-gain rectification. A-SSCC Guang Zhu, Quan Pan, John Zhuang, Charlie Zhi, C. Patrick Yue
2015	—	`conf`	A 60GHz 4Gb/s fully integrated NRZ-to-QPSK modulator SoC for backhaul links in fiber-wireless networks. ESSCIRC Yipeng Wang, Duona Luo, Quan Pan, Liwen Jing, Zhixin Li, C. Patrick Yue
2015	J	`jnl`	A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection. IEEE Trans. Circuits Syst. I Regul. Pap. Yan Lu, Yipeng Wang, Quan Pan, Wing-Hung Ki, C. Patrick Yue
2014	J	`jnl`	A 26-28-Gb/s Full-Rate Clock and Data Recovery Circuit With Embedded Equalizer in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Li Sun, Quan Pan, Keh-Chung Wang, C. Patrick Yue
2014	—	`conf`	A 41-mW 30-Gb/s CMOS optical receiver with digitally-tunable cascaded equalization. ESSCIRC Quan Pan, Yipeng Wang, Zhengxiong Hou, Li Sun, Liang Wu, Wing-Hung Ki, Patrick Chiang, C. Patrick Yue
2014	—	`conf`	A 48-mW 18-Gb/s fully integrated CMOS optical receiver with photodetector and adaptive equalizer. VLSIC Quan Pan, Zhengxiong Hou, Yipeng Wang, Yan Lu, Wing-Hung Ki, Keh-Chung Wang, C. Patrick Yue
2013	—	`conf`	A 25-Gb/s 32.1-dB CMOS limiting amplifier for integrated optical receivers. ASICON Zhengxiong Hou, Yipeng Wang, Quan Pan, C. Patrick Yue
2013	—	`conf`	A 65-nm CMOS P-well/Deep N-well avalanche photodetector for integrated 850-nm optical. ASICON Quan Pan, Zhengxiong Hou, Yipeng Wang, C. Patrick Yue