Qingchuan Shi

12 papers B 1C 3Journal 6Unranked 2
YearRankTypeTitle / Venue / Authors
2018 C conf
CSSMT: Compiler Based Software Simultaneous Multithreading (SMT).
PDP
Yuanfang Chen, Qingchuan Shi, Xiaoming Li
2018 J jnl
Declarative Resilience: A Holistic Soft-Error Resilient Multicore Architecture that Trades off Program Accuracy for Efficiency.
ACM Trans. Embed. Comput. Syst.
Hamza Omar, Qingchuan Shi, Masab Ahmad, Halit Dogan, Omer Khan
2017 J jnl
Exploiting the Tradeoff between Program Accuracy and Soft-error Resiliency Overhead for Machine Learning Workloads.
CoRR
Qingchuan Shi, Hamza Omar, Omer Khan
2016 J jnl
LDAC: Locality-Aware Data Access Control for Large-Scale Multicore Cache Hierarchies.
ACM Trans. Archit. Code Optim.
Qingchuan Shi, George Kurian, Farrukh Hijaz, Srinivas Devadas, Omer Khan
2016 J jnl
Locality-aware data replication in the last-level cache for large scale multicores.
J. Supercomput.
Farrukh Hijaz, Qingchuan Shi, George Kurian, Srinivas Devadas, Omer Khan
2015 J jnl
A Cross-Layer Multicore Architecture to Tradeoff Program Accuracy and Resilience Overheads.
IEEE Comput. Archit. Lett.
Qingchuan Shi, Henry Hoffmann, Omer Khan
2015 — conf
CRONO: A Benchmark Suite for Multithreaded Graph Algorithms Executing on Futuristic Multicores.
IISWC
Masab Ahmad, Farrukh Hijaz, Qingchuan Shi, Omer Khan
2015 B conf
OSPREY: Implementation of Memory Consistency Models for Cache Coherence Protocols involving Invalidation-Free Data Access.
PACT
George Kurian, Qingchuan Shi, Srinivas Devadas, Omer Khan
2013 C conf
A private level-1 cache architecture to exploit the latency and capacity tradeoffs in multicores operating at near-threshold voltages.
ICCD
Farrukh Hijaz, Qingchuan Shi, Omer Khan
2013 J jnl
Toward Holistic Soft-Error-Resilient Shared-Memory Multicores.
Computer
Qingchuan Shi, Omer Khan
2013 C conf
Towards efficient dynamic data placement in NoC-based multicores.
ICCD
Qingchuan Shi, Farrukh Hijaz, Omer Khan
2012 — conf
Low-Latency Mechanisms for Near-Threshold Operation of Private Caches in Shared Memory Multicores.
MICRO Workshops
Farrukh Hijaz, Qingchuan Shi, Omer Khan