Qing Dong

18 papers A 1C 2Journal 6Unranked 9
YearRankTypeTitle / Venue / Authors
2016 J jnl
DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout.
ACM Trans. Design Autom. Electr. Syst.
Gong Chen, Toru Fujimura, Qing Dong, Shigetoshi Nakatake, Bo Yang
2015 J jnl
Layout Dependent Effect-Aware Leakage Current Reduction and Its Application to Low-Power SAR-ADC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Gong Chen, Yu Zhang, Qing Dong, Mingyu Li, Shigetoshi Nakatake
2015 — conf
Low-Power and Low-Variability Programmable Delay Element and Its Application to Post-Silicon Skew Tuning.
ISVLSI
Daijiro Murooka, Yu Zhang, Qing Dong, Shigetoshi Nakatake
2013 — conf
A 9-bit 50msps SAR ADC with pre-charge VCM -based double input range algorithm.
ACM Great Lakes Symposium on VLSI
Gong Chen, Bo Yang, Yu Zhang, Qing Dong, Shigetoshi Nakatake
2013 — conf
A comparator energy model considering shallow trench isolation stress by geometric programming.
ISQED
Gong Chen, Yu Zhang, Bo Yang, Qing Dong, Shigetoshi Nakatake
2013 J jnl
Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yu Zhang, Gong Chen, Bo Yang, Jing Li, Qing Dong, Mingyu Li, Shigetoshi Nakatake
2013 C conf
Performance-driven SRAM macro design with parameterized cell considering layout-dependent effects.
VLSI-SoC
Yu Zhang, Gong Chen, Qing Dong, Mingyu Li, Shigetoshi Nakatake
2013 J jnl
Structured Analog Circuit and Layout Design with Transistor Array.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake
2012 — conf
Transistor channel decomposition for structured analog layout, manufacturability and low-power applications.
ISQED
Qing Dong, Bo Yang, Gong Chen, Jing Li, Shigetoshi Nakatake
2011 — conf
Layout-aware mismatch modeling for CMOS current sources with D/A converter analysis.
ISQED
Bo Liu, Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake
2011 — conf
Layout-aware variation evaluation of analog circuits and its validity on op-amp designs.
ACM Great Lakes Symposium on VLSI
Kota Shinohara, Mihoko Hidaka, Jing Li, Qing Dong, Bo Yang, Shigetoshi Nakatake
2010 C conf
Post-placement STI well width adjusting by geometric programming for device mobility enhancement in critical path.
ISCAS
Jing Li, Bo Yang, Qing Dong, Shigetoshi Nakatake
2010 A conf
Structured analog circuit design and MOS transistor decomposition for high accuracy applications.
ICCAD
Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake
2009 J jnl
Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake
2009 — conf
Incremental buffer insertion and module resizing algorithm using geometric programming.
ACM Great Lakes Symposium on VLSI
Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake
2009 — conf
STI stress aware placement optimization based on geometric programming.
ACM Great Lakes Symposium on VLSI
Jing Li, Bo Yang, Xiaochuan Hu, Qing Dong, Shigetoshi Nakatake
2009 J jnl
Structured Placement with Topological Regularity Evaluation.
IPSJ Trans. Syst. LSI Des. Methodol.
Qing Dong, Shigetoshi Nakatake
2008 — conf
Constraint-free analog placement with topological symmetry structure.
ASP-DAC
Qing Dong, Shigetoshi Nakatake