Qin Wang

81 papers A* 4A 3B 3C 10Journal 37Unranked 24
YearRankTypeTitle / Venue / Authors
2026 J jnl
A power-efficient multiplier with fine-grained power management.
Microelectron. J.
Tong Li, Honglan Jiang, Qin Wang, Jianfei Jiang, Zhigang Mao
2026 J jnl
LUT-ALMs: Trading Off Accuracy and Power for Approximate Logarithmic Multipliers via LUT Optimization.
IEEE Trans. Computers
Wenhui Zhang, Xinkuang Geng, Xiaolu Hu, Hui Wang, Jianfei Jiang, Qin Wang, Siting Liu, Jie Han, Honglan Jiang
2026 J jnl
Leveraging Tensor Dataflow for Improved Thermal Performance on 3D-Stacked SRAM Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pengyu Liu, Liyan Chen, Zelong Yuan, Yingkun Liu, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2026 J jnl
Signal integrity-aware multi-path design workflow for ultra-large-scale three-dimensional chips: A logic-on-memory stacking case study.
Microelectron. J.
Ang Li, Jianfei Jiang, Naifeng Jing, Yanan Sun, Zhigang Mao, Qin Wang
2026 — conf
Viper: An ILP-Based Vectorization Framework for Fully Homomorphic Encryption.
ASP-DAC
Weidong Yang, Xinmo Li, Xiangmin Guo, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao, Weiguang Sheng
2025 J jnl
A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip.
IEEE Trans. Very Large Scale Integr. Syst.
Zizheng Dong, Shuaipeng Li, Weijia Zhu, Ang Li, Qin Wang, Naifeng Jing, Weiguang Sheng, Jianfei Jiang, Zhigang Mao
2025 A* conf
AsyncDIMM: Achieving Asynchronous Execution in DIMM-Based Near-Memory Processing.
HPCA
Liyan Chen, Dongxu Lyu, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2025 A* conf
AttenPIM: Accelerating LLM Attention with Dual-mode GEMV in Processing-in-Memory.
DAC
Liyan Chen, Dongxu Lyu, Zhenyu Li, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2025 J jnl
Bridge-NDP: Efficient Communication-Computation Overlap in Near Data Processing System.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Liyan Chen, Pengyu Liu, Dongxu Lyu, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2025 J jnl
Efficient Die-to-Die Communication: UCIe Link Simulation and Optimization in a Chiplet-Based System.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Kunyue Li, Shuaipeng Li, Xiaoyan Li, Zizheng Dong, Sai Gao, Jialei Sun, Naifeng Jing, Qin Wang, Guanghui He, Jianfei Jiang
2025 J jnl
Efficient Extraction and Packing Modules for Posit Multipliers.
IEEE Trans. Circuits Syst. II Express Briefs
Tong Li, Honglan Jiang, Zhou Wang, Qin Wang, Jianfei Jiang, Zhigang Mao
2025 A conf
HEILP: An ILP-Based Scale Management Method for Homomorphic Encryption Compiler.
DATE
Weidong Yang, Shuya Ji, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao, Weiguang Sheng
2025 J jnl
Low-Power Multiplier Designs by Leveraging Correlations of 2$\times$×2 Encoded Partial Products.
IEEE Trans. Computers
Ao liu, Siting Liu, Hui Wang, Qin Wang, Fabrizio Lombardi, Zhigang Mao, Honglan Jiang
2025 J jnl
MACS: A Multidomain Collaborative Adaptive Clock Scheme for Large-Scale Reconfigurable Dataflow Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shuya Ji, Weidong Yang, Jianfei Jiang, Naifeng Jing, Honglan Jiang, Zhigang Mao, Qin Wang
2025 — conf
MDNMP: Metapath-Driven Software-Hardware Co-Design for HGNN Acceleration with Near-Memory Processing.
ASP-DAC
Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2025 A* conf
Principle-based Dataflow Optimization for Communication Lower Bound in Operator-Fused Tensor Accelerator.
DAC
Lei Xu, Chen Yin, Zelong Yuan, Weiguang Sheng, Jianfei Jiang, Qin Wang, Naifeng Jing
2025 C conf
RVME: An Efficient Matrix Engine Design Based on Matrix Extension of RISC-V.
ICCD
Wanqi Chen, Weidong Yang, Yiming Guo, Jing Qiu, Renpei Wang, Jianfei Jiang, Naifeng Jing, Qin Wang
2025 J jnl
Robust Monolithic 3D Carbon-Based Computing-in-SRAM With Variation-Aware Bit-Wise Data-Mapping for High-Performance and Integration Density.
IEEE Trans. Circuits Syst. I Regul. Pap.
Dengfeng Wang, Weifeng He, Qin Wang, Hailong Jiao, Yanan Sun
2024 J jnl
3A-ReRAM: Adaptive Activation Accumulation in ReRAM-Based CNN Accelerator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zihan Zhang, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2024 C conf
A 0.8-ps RMS Precision Period Jitter Measurement Circuit with Offset Reduction.
ISCAS
Lin Xie, Zizheng Dong, Jialei Sun, Sai Gao, Shuaipeng Li, Naifeng Jing, Qin Wang, Jianfei Jiang
2024 J jnl
A Comprehensive Dataflow-Mapping Optimization for Fully Pipelined Execution in Spatial Programmable Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pengyu Liu, Ang Li, Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2024 — conf
A Low-Power and High-Accuracy Approximate Adder for Logarithmic Number System.
ACM Great Lakes Symposium on VLSI
Wenhui Zhang, Xinkuang Geng, Qin Wang, Jie Han, Honglan Jiang
2024 J jnl
A novel vehicle collision detection system: Integrating audio-visual fusion for enhanced performance.
Expert Syst. Appl.
Kunyue Li, Zhengji Zhao, Qixuan Cai, Qin Wang, Naifeng Jing, Zhigang Mao, Jianfei Jiang
2024 J jnl
An Architectural Error Metric for CNN-Oriented Approximate Multipliers.
CoRR
Ao liu, Jie Han, Qin Wang, Zhigang Mao, Honglan Jiang
2024 B conf
Bridge-NDP: Achieving Efficient Communication-Computation Overlap in Near Data Processing with Bridge Architecture.
ASPDAC
Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2024 J jnl
DeltaGNN: Accelerating Graph Neural Networks on Dynamic Graphs With Delta Updating.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chen Yin, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2024 A* conf
Enabling Multiple Tensor-wise Operator Fusion for Transformer Models on Spatial Accelerators.
DAC
Lei Xu, Zhiwen Mo, Qin Wang, Jianfei Jiang, Naifeng Jing
2024 J jnl
RecPIM: Efficient In-Memory Processing for Personalized Recommendation Inference Using Near-Bank Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Weidong Yang, Yuqing Yang, Shuya Ji, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao, Weiguang Sheng
2024 B conf
SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network Acceleration.
ASPDAC
Chen Yin, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2024 — conf
VDA: A Simple but Efficient Virtual-Channel-Based Deadlock Avoidance Scheme for Scalable Chiplet Networks.
ACM Great Lakes Symposium on VLSI
Duo Yu, Ang Li, Naifeng Jing, Jianfei Jiang, Weiguang Sheng, Qin Wang
2023 J jnl
A Reschedulable Dataflow-SIMD Execution for Increased Utilization in CGRA Cross-Domain Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chen Yin, Naifeng Jing, Jianfei Jiang, Qin Wang, Zhigang Mao
2023 J jnl
A Unified Clock-Gated Error Correction Scheme With Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router.
IEEE Trans. Circuits Syst. II Express Briefs
Bingxi Pei, Shi Xu, Zhang Luo, Qin Wang, Mingche Lai, Weifeng He
2023 C conf
ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors.
ICCD
Shuya Ji, Weidong Yang, Jianfei Jiang, Naifeng Jing, Weiguang Sheng, Ang Li, Qin Wang
2023 — conf
An Efficient near-Bank Processing Architecture for Personalized Recommendation System.
ASP-DAC
Yuqing Yang, Weidong Yang, Qin Wang, Naifeng Jing, Jianfei Jiang, Zhigang Mao, Weiguang Sheng
2023 — conf
An NoC-based CNN Accelerator for Edge Computing.
ASICON
Jianing Gao, Qiming Shao, Fangyu Deng, Qin Wang, Naifeng Jing, Jianfei Jiang
2023 J jnl
BC-MVLiM: A Binary-Compatible Multi-Valued Logic-in-Memory Based on Memristive Crossbars.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yanan Sun, Zhi Li, Weiyi Liu, Weifeng He, Qin Wang, Zhigang Mao
2023 J jnl
Exploiting bit sparsity in both activation and weight in neural networks accelerators.
Integr.
Naifeng Jing, Zihan Zhang, Yongshuai Sun, Pengyu Liu, Liyan Chen, Qin Wang, Jianfei Jiang
2023 — conf
High-Performance Genomic Analysis Heterogeneous System Using OpenCL.
ASICON
Jianing Gao, Lingyi Liu, Qin Wang, Naifeng Jing, Jianfei Jiang
2023 B conf
Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture.
FPL
Pengyu Liu, Zihan Zhang, Chen Yin, Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2023 — conf
RTMDet-R2: An Improved Real-Time Rotated Object Detector.
PRCV (12)
Haifeng Xiang, Naifeng Jing, Jianfei Jiang, Hongbo Guo, Weiguang Sheng, Zhigang Mao, Qin Wang
2023 — conf
ReMap: Reorder Mapping for Multi-level Uneven Distribution on Sparse ReRAM Accelerator.
ASICON
Zhuo Chen, Zihan Zhang, Jianfei Jiang, Weiguang Sheng, Qin Wang, Naifeng Jing
2022 J jnl
A Low Coupling and Lightweight Algorithm for Ship Detection in Optical Remote Sensing Images.
IEEE Geosci. Remote. Sens. Lett.
Guochao Deng, Qin Wang, Jianfei Jiang, Qirun Hong, Naifeng Jing, Weiguang Sheng, Zhigang Mao
2022 J jnl
A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator.
ACM Trans. Design Autom. Electr. Syst.
Taozhong Li, Naifeng Jing, Jianfei Jiang, Qin Wang, Zhigang Mao, Yiran Chen
2022 J jnl
A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zihan Zhang, Jianfei Jiang, Yongxin Zhu, Qin Wang, Zhigang Mao, Naifeng Jing
2022 J jnl
An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs.
IEEE Trans. Very Large Scale Integr. Syst.
Shengzhao Li, Qin Wang, Jianfei Jiang, Weiguang Sheng, Naifeng Jing, Zhigang Mao
2022 — conf
Boosting ReRAM-based DNN by Row Activation Oversubscription.
ASP-DAC
Mengyu Guo, Zihan Zhang, Jianfei Jiang, Qin Wang, Naifeng Jing
2022 J jnl
Hierarchical photoelectric hybrid packet switching network for high-performance computing.
JOCN
Bingxi Pei, Shi Xu, Zhang Luo, Qin Wang, Mingche Lai, Wei-Feng He
2021 — conf
A Mapping Method for Reconfigurable Array based on Decoupled DataFlow.
BigDataSecurity
Zihan Zhang, Jianfei Jiang, Weiguang Sheng, Qin Wang, Zhigang Mao, Naifeng Jing
2021 C conf
Design of Ternary Logic-in-Memory Based on Memristive Dual-Crossbars.
ISCAS
Weiyi Liu, Yanan Sun, Weifeng He, Qin Wang
2021 C conf
Fast FPGA-Based Emulation for ReRAM-Enabled Deep Neural Network Accelerator.
ISCAS
Yongquan Shi, Yongshuai Sun, Jianfei Jiang, Guanghui He, Qin Wang, Naifeng Jing
2021 A conf
Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture.
DATE
Chen Yin, Qin Wang, Jianfei Jiang, Weiguang Sheng, Guanghui He, Zhigang Mao, Naifeng Jing
2020 C conf
Decoupling the Multi-Rate Dataflow Execution in Coarse-Grained Reconfigurable Array.
ISCAS
Tu Hong, Ning Guan, Chen Yin, Qin Wang, Jianfei Jiang, Jing Jin, Guanghui He, Naifeng Jing
2020 — conf
Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration.
ACM Great Lakes Symposium on VLSI
Zihan Zhang, Taozhong Li, Ning Guan, Qin Wang, Guanghui He, Weiguang Sheng, Zhigang Mao, Naifeng Jing
2020 — conf
Frequency Attention Network: Blind Noise Removal for Real Images.
ACCV (2)
Hongcheng Mo, Jianfei Jiang, Qin Wang, Dong Yin, Pengyu Dong, Jingjun Tian
2020 J jnl
Priority Branches for Ship Detection in Optical Remote Sensing Images.
Remote. Sens.
Yijia Zhang, Weiguang Sheng, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao
2020 J jnl
Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling.
IEEE Trans. Parallel Distributed Syst.
Zhongyuan Zhao, Weiguang Sheng, Qin Wang, Wenzhi Yin, Pengfei Ye, Jinchao Li, Zhigang Mao
2019 — conf
A New Approximate Multiplier Design for Digital Signal Processing.
ASICON
Yue Zhao, Tong Li, Feng Dong, Qin Wang, Weifeng He, Jianfei Jiang
2019 J jnl
A New Cellular-Based Redundant TSV Structure for Clustered Faults.
IEEE Trans. Very Large Scale Integr. Syst.
Qin Wang, Zechen Liu, Jianfei Jiang, Naifeng Jing, Weiguang Sheng
2019 J jnl
A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations.
ACM Trans. Design Autom. Electr. Syst.
Taozhong Li, Qin Wang, Yongxin Zhu, Jianfei Jiang, Guanghui He, Jing Jin, Zhigang Mao, Naifeng Jing
2019 C conf
A Rapid Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs.
ISCAS
Sijie Zheng, Hongjun You, Guanghui He, Qin Wang, Tao Si, Jianfei Jiang, Jing Jin, Naifeng Jing
2019 J jnl
Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells.
IEEE Trans. Circuits Syst. II Express Briefs
Yanan Sun, Jiawei Gu, Weifeng He, Qin Wang, Naifeng Jing, Zhigang Mao, Weikang Qian, Li Jiang
2019 J jnl
Lung Nodule Detection in CT Images Using a Raw Patch-Based Convolutional Neural Network.
J. Digit. Imaging
Qin Wang, Fengyi Shen, Linyao Shen, Jia Huang, Weiguang Sheng
2019 J jnl
Scale Adaptive Proposal Network for Object Detection in Remote Sensing Images.
IEEE Geosci. Remote. Sens. Lett.
Shuo Zhang, Guanghui He, Hai-Bao Chen, Naifeng Jing, Qin Wang
2018 J jnl
IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs.
IEEE Trans. Parallel Distributed Syst.
Jianfei Wang, Qin Wang, Li Jiang, Chao Li, Xiaoyao Liang, Naifeng Jing
2018 — conf
MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs.
ReConFig
Shuai Xie, Zhongyuan Zhao, Weiguang Sheng, Qin Wang, Zhigang Mao
2018 A conf
Optimizing the data placement and transformation for multi-bank CGRA computing system.
DATE
Zhongyuan Zhao, Yantao Liu, Weiguang Sheng, Tushar Krishna, Qin Wang, Zhigang Mao
2017 — conf
A metastability-based true random number generator on FPGA.
ASICON
Chaoyang Li, Qin Wang, Jianfei Jiang, Nin Guan
2017 — conf
An on-chip circuit for timing measurement of SRAM IP.
ASICON
Xianjie Long, Qin Wang, Jianfei Jiang, Nin Guan
2017 J jnl
Dynamic data split: A crosstalk suppression scheme in TSV-based 3D IC.
Integr.
Qin Wang, Zhenyang Chen, Jianfei Jiang, Zheng Guo, Zhigang Mao
2016 J jnl
Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects.
J. Circuits Syst. Comput.
Jianfei Jiang, Zhigang Mao, Weiguang Sheng, Qin Wang, Weifeng He
2015 C conf
A Circuit Design of SMS4 against Chosen Plaintext Attack.
CIS
Jiachao Chen, Qin Wang, Zheng Guo, Junrong Liu, Haihua Gu
2015 — conf
A contactless testing methodology for pre-bond interposer.
MWSCAS
Jianfei Jiang, Weiguang Sheng, Qin Wang, Zhigang Mao
2015 — conf
A crosstalk avoidance scheme based on re-layout of signal TSV.
ASICON
Jiayi Hu, Qin Wang, Jianfei Jiang, Jing Xie, Zhigang Mao
2015 J jnl
Design optimization for capacitive-resistively driven on-chip global interconnect.
IEICE Electron. Express
Jianfei Jiang, Weifeng He, Jizeng Wei, Qin Wang, Zhigang Mao
2015 — conf
Fault detection and redundancy design for TSVs in 3D ICs.
ASICON
Sai Hu, Qin Wang, Zheng Guo, Jing Xie, Zhigang Mao
2013 C conf
Modeling and analysis of signal transmission with Through Silicon Via (TSV) noise coupling.
ISCAS
Zhenyang Chen, Qin Wang, Jing Xie, Jin Tian, Jianfei Jiang, Yufei Li, Wen Yin
2013 — conf
TSVs-aware floorplanning for 3D integrated circuit.
ASICON
Jieliang Lu, Qin Wang, Jing Xie, Zhigang Mao
2012 — conf
A Case Study of CPNS Intelligence: Provenance Reasoning over Tracing Cross Contamination in Food Supply Chain.
ICDCS Workshops
Shunqing Yan, Yongxin Zhu, Qiannan Zhang, Qin Wang, Ming Ni, Guangwei Xie
2012 — conf
Group-Based Fast Mode Decision Algorithm for Intra Prediction in HEVC.
SITIS
Shunqing Yan, Liang Hong, Weifeng He, Qin Wang
2011 — conf
A new asynchronous delay-insensitive link based on a 1-of-4 LETS code.
ASICON
Can Wang, Qin Wang, Jianfei Jiang
2011 C conf
Effective multi-standard macroblock prediction VLSI design for reconfigurable multimedia systems.
ISCAS
Yuliang Tao, Guanghui He, Weifeng He, Qin Wang, Jun Ma, Zhigang Mao