Qicheng Yu - RankMe

12 papers A 1C 2Journal 4Unranked 4

Year	Rank	Type	Title / Venue / Authors
2022	—	`conf`	Proactive Chatbot Framework Based on the PS2CLH Model: An AI-Deep Learning Chatbot Assistant for Students. IntelliSys (1) Arlindo Almada, Qicheng Yu, Preeti Patel
2017	—	`conf`	16.7 A 12b 10GS/s interleaved pipeline ADC in 28nm CMOS technology. ISSCC Siddharth Devarajan, Larry Singer, Dan Kelly, Steve Kosic, Tao Pan, José B. Silva, Janet Brunsilius, Daniel Rey-Losada, Frank Murden, Carroll Speir, Jeff Bray, Eric Otte, Nevena Rakuljic, Phil Brown, Todd Weigandt, Qicheng Yu, Donald Paterson, Corey Petersen, Jeffrey C. Gealow
2017	J	`jnl`	A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology. IEEE J. Solid State Circuits Siddharth Devarajan, Larry Singer, Dan Kelly, Tao Pan, José B. Silva, Janet Brunsilius, Daniel Rey-Losada, Frank Murden, Carroll Speir, Jeff Bray, Eric Otte, Nevena Rakuljic, Phil Brown, Todd Weigandt, Qicheng Yu, Donald Paterson, Corey Petersen, Jeffrey C. Gealow, Gabriele Manganaro
2016	—	`conf`	A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither. VLSI Circuits Ahmed M. A. Ali, Hüseyin Dinc, Paritosh Bhoraskar, Scott Puckett, Andy Morgan, Ning Zhu, Qicheng Yu, Christopher Dillon, Bryce Gray, Jonathan Lanford, Matthew McShea, Ushma Mehta, Scott Bardsley, Peter R. Derounian, Ryan Bunch, Ralph Moore, Gerry Taylor
2014	C	`conf`	Web service based Grid workflow application in quantitative remote sensing retrieval. IGARSS Longli Liu, Yong Xue, Jingzun Zhang, Jia Liu, Qicheng Yu, Chi Li
2012	—	`—`	An agent-based adaptive join algorithm for building data warehouses. Qicheng Yu
2006	J	`jnl`	A 2.5-Gb/s Multi-Rate 0.25-$\mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition. IEEE J. Solid State Circuits Michael H. Perrott, Yunteng Huang, Rex T. Baird, Bruno W. Garlepp, Douglas Pastorello, Eric T. King, Qicheng Yu, Dan B. Kasha, Philip Steiner, Ligang Zhang, Jerrell P. Hein, Bruce Del Signore
1997	J	`jnl`	Efficient approximation of symbolic network functions using matroid intersection algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qicheng Yu, Carl Sechen
1996	J	`jnl`	Generation of colour-constrained spanning trees with application in symbolic circuit analysis. Int. J. Circuit Theory Appl. Qicheng Yu, Carl Sechen
1995	C	`conf`	Efficient Approximation of Symbolic Network Function Using Matroid Intersection Algorithms. ISCAS Qicheng Yu, Carl Sechen
1994	A	`conf`	Approximate symbolic analysis of large analog integrated circuits. ICCAD Qicheng Yu, Carl Sechen
1994	—	`conf`	Generation of color-constrained spanning trees with application in symbolic circuit analysis. Great Lakes Symposium on VLSI Qicheng Yu, Carl Sechen