Qiaochu Zhang - RankMe

24 papers A* 2A 4B 1Journal 8Unranked 9

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Correction to: Ensuring the exercise of human agency in AI-based military systems: concerns across the lifecycle. Ethics Inf. Technol. Ingvild Bode, Anna Nadibaidze, Tom F. A. Watts, Qiaochu Zhang
2026	J	`jnl`	MLKCP-MIL: Multi-scale large-kernel convolution and positional encoding-based multiple instance learning for glandular histopathology whole slide image classification. Biomed. Signal Process. Control. Xiayi Yang, Qiaochu Zhang, Xuelian Gu, Hongzheng Ren, Wenxu Gong, Rong Liao, Jiale Dong, Ping Li, Yurong Tao
2025	J	`jnl`	Ensuring the exercise of human agency in AI-based military systems: concerns across the lifecycle. Ethics Inf. Technol. Ingvild Bode, Anna Nadibaidze, Tom F. A. Watts, Qiaochu Zhang
2025	J	`jnl`	Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adders. IEEE J. Solid State Circuits Shiyu Su, Qiaochu Zhang, Baishakhi Rani Biswas, Sandeep K. Gupta, Mike Shuo-Wei Chen
2024	A	`conf`	A Novel Multi-Objective Optimization Framework for Analog Circuit Customization. DATE Mutian Zhu, Mohsen Hassanpourghadi, Qiaochu Zhang, Mike Shuo-Wei Chen, Anthony F. J. Levi, Sandeep Gupta
2024	—	`conf`	A Stochastic Analog SAT Solver in 65nm CMOS Achieving 6.6μs Average Solution Time with 100% Solvability for Hard 3-SAT Problems. VLSI Technology and Circuits Qiaochu Zhang, Shiyu Su, Zerui Liu, Hsiang-Chun Cheng, Zhengyi Qiu, Mayank Palaria, Jiacheng Ye, Deming Meng, Buyun Chen, Sushmit Hossain, Wei Wu, Mike Shuo-Wei Chen
2024	J	`jnl`	Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration. IEEE J. Solid State Circuits Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su, Mike Shuo-Wei Chen
2024	—	`conf`	Synthesizable 10-bit Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adder with 0.012mm VLSI Technology and Circuits Qiaochu Zhang, Shiyu Su, Baishakhi Rani Biswas, Sandeep Gupta, Mike Shuo-Wei Chen
2023	—	`conf`	A 2GS/s 8.5-Bit Time-Based ADC using a Segmented Stochastic Flash TDC. CICC Shiyu Su, Qiaochu Zhang, Mike Shuo-Wei Chen
2023	—	`conf`	A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving -67dBc Fractional Spur. ISSCC Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su, Mike Shuo-Wei Chen
2023	—	`conf`	A Memristor-Based Analog Accelerator for Solving Quadratic Programming Problems. CICC Hsiang-Chun Cheng, Shiyu Su, Mayank Palaria, Qiaochu Zhang, Ce Yang, Sushmit Hossain, Ryan M. Bena, Buyun Chen, Zerui Liu, Juzheng Liu, Rezwan A. Rasul, Quan Nguyen, Wei Wu, Mike Shuo-Wei Chen
2023	—	`conf`	Analog Kalman Filter with Integration and Digitization via a Shared Thyristor-Based VCO for Sensor Fusion in 65 nm CMOS. ESSCIRC Mayank Palaria, Shiyu Su, Hsiang-Chun Cheng, Rezwan A. Rasul, Qiaochu Zhang, Soumya Mahapatra, Chong-Fatt Law, Sushmit Hossain, Ryan M. Bena, Wei Wu, Quan Nguyen, Mike Shuo-Wei Chen
2022	J	`jnl`	A Fractional-N Digital MDLL With Background Two-Point DTC Calibration. IEEE J. Solid State Circuits Qiaochu Zhang, Shiyu Su, Cheng-Ru Ho, Mike Shuo-Wei Chen
2022	A*	`conf`	A cost-efficient fully synthesizable stochastic time-to-digital converter design based on integral nonlinearity scrambling. DAC Qiaochu Zhang, Shiyu Su, Mike Shuo-Wei Chen
2022	—	`conf`	Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms. ASP-DAC Shiyu Su, Qiaochu Zhang, Mohsen Hassanpourghadi, Juzheng Liu, Rezwan A. Rasul, Mike Shuo-Wei Chen
2022	—	`conf`	TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture. ASP-DAC Shiyu Su, Qiaochu Zhang, Juzheng Liu, Mohsen Hassanpourghadi, Rezwan A. Rasul, Mike Shuo-Wei Chen
2021	—	`conf`	29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur. ISSCC Qiaochu Zhang, Shiyu Su, Cheng-Ru Ho, Mike Shuo-Wei Chen
2021	J	`jnl`	Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms. CoRR Shiyu Su, Qiaochu Zhang, Mohsen Hassanpourghadi, Juzheng Liu, Rezwan A. Rasul, Mike Shuo-Wei Chen
2021	A*	`conf`	Circuit Connectivity Inspired Neural Network for Analog Mixed-Signal Functional Modeling. DAC Mohsen Hassanpourghadi, Shiyu Su, Rezwan A. Rasul, Juzheng Liu, Qiaochu Zhang, Mike Shuo-Wei Chen
2021	A	`conf`	From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. ICCAD Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan A. Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, Mike Shuo-Wei Chen
2021	J	`jnl`	TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture. CoRR Shiyu Su, Qiaochu Zhang, Juzheng Liu, Mohsen Hassanpourghadi, Rezwan A. Rasul, Mike Shuo-Wei Chen
2020	A	`conf`	CEPA: CNN-based Early Performance Assertion Scheme for Analog and Mixed-Signal Circuit Simulation. ICCAD Qiaochu Zhang, Shiyu Su, Juzheng Liu, Mike Shuo-Wei Chen
2020	A	`conf`	Transfer Learning with Bayesian Optimization-Aided Sampling for Efficient AMS Circuit Modeling. ICCAD Juzheng Liu, Mohsen Hassanpourghadi, Qiaochu Zhang, Shiyu Su, Mike Shuo-Wei Chen
2019	B	`conf`	Is hippocampus getting bumpier with age: a quantitative analysis of fine-scale dentational feature under the hippocampus on 552 healthy subjects. Image Processing Shuxiu Cai, Xiaxia Yu, Qiaochu Zhang, Chuan Huang, Yi Gao