Qianming Yang

21 papers A 2C 4Misc 1Journal 9Unranked 5
YearRankTypeTitle / Venue / Authors
2024 J jnl
A Low-Cost Floating-Point Dot-Product-Dual-Accumulate Architecture for HPC-Enabled AI.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hongbing Tan, Libo Huang, Zhong Zheng, Hui Guo, Qianming Yang, Li Shen, Gang Chen, Liquan Xiao, Nong Xiao
2023 — conf
Low-Cost Multiple-Precision Multiplication Unit Design For Deep Learning.
ACM Great Lakes Symposium on VLSI
Jing Zhang, Libo Huang, Hongbing Tan, Ling Yang, Zhong Zheng, Qianming Yang
2022 C conf
Efficient Multiple-Precision and Mixed-Precision Floating-Point Fused Multiply-Accumulate Unit for HPC and AI Applications.
ICA3PP
Hongbing Tan, Run Yan, Ling Yang, Libo Huang, Liquan Xiao, Qianming Yang
2020 J jnl
P4 to FPGA-A Fast Approach for Generating Efficient Network Processors.
IEEE Access
Zhuang Cao, Huayou Su, Qianming Yang, Junzhong Shen, Mei Wen, Chunyuan Zhang
2019 — conf
Poster Abstract: A Template-based Framework for Generating Network Processor in FPGA.
INFOCOM Workshops
Zhuang Cao, Huayou Su, Qianming Yang, Mei Wen, Chunyuan Zhang
2017 J jnl
FPGA-accelerated deep convolutional neural networks for high throughput and energy efficiency.
Concurr. Comput. Pract. Exp.
Yuran Qiao, Junzhong Shen, Tao Xiao, Qianming Yang, Mei Wen, Chunyuan Zhang
2017 C conf
Optimizing OpenCL Implementation of Deep Convolutional Neural Network on FPGA.
NPC
Yuran Qiao, Junzhong Shen, Dafei Huang, Qianming Yang, Mei Wen, Chunyuan Zhang
2015 J jnl
Enabling a Uniform OpenCL Device View for Heterogeneous Platforms.
IEICE Trans. Inf. Syst.
Dafei Huang, Changqing Xun, Nan Wu, Mei Wen, Chunyuan Zhang, Xing Cai, Qianming Yang
2015 — conf
Unified Virtual Memory Support for Deep CNN Accelerator on SoC FPGA.
ICA3PP (1)
Tao Xiao, Yuran Qiao, Junzhong Shen, Qianming Yang, Mei Wen
2013 J jnl
Accelerating thread-intensive and explicit memory management programs with dynamic partial reconfiguration.
J. Supercomput.
Qianming Yang, Mei Wen, Nan Wu, Chunyuan Zhang
2013 J jnl
SIR: A Secure Identifier-Based Inter-Domain Routing for Identifier/Locator Split Network.
IEICE Trans. Commun.
Yaping Liu, Zhihong Liu, Baosheng Wang, Qianming Yang
2013 J jnl
Simulating Cardiac Electrophysiology in the Era of GPU-Cluster Computing.
IEICE Trans. Inf. Syst.
Jun Chai, Mei Wen, Nan Wu, Dafei Huang, Jing Yang, Xing Cai, Chunyuan Zhang, Qianming Yang
2012 — conf
Fully Distributed On-chip Instruction Memory Design for Stream Architecture Based on Field-Divided VLIW Compression.
HPCC-ICESS
Yi He, Maolin Guan, Chunyuan Zhang, Tian Tian, Qianming Yang
2012 A conf
The masala machine: accelerating thread-intensive and explicit memory management programs with dynamically reconfigurable FPGAs (abstract only).
FPGA
Mei Wen, Nan Wu, Qianming Yang, Chunyuan Zhang, Liang Zhao
2011 J jnl
Tiled Multi-Core Stream Architecture.
Trans. High Perform. Embed. Archit. Compil.
Nan Wu, Qianming Yang, Mei Wen, Yi He, Ju Ren, Maolin Guan, Chunyuan Zhang
2010 C conf
SAT: A Stream Architecture Template for Embedded Applications.
CIT
Qianming Yang, Nan Wu, Mei Wen, Yi He, Huayou Su, Chunyuan Zhang
2010 C conf
Software Managed Instruction Scratchpad Memory Optimization in Stream Architecture Based on Hot Code Analysis of Kernels.
DSD
Yi He, Ju Ren, Mei Wen, Qianming Yang, Nan Wu, Chunyuan Zhang
2008 A conf
FPGA-based Equivalent Simulation Technology (FEST) for clustered stream architecture.
ACSAC
Yi He, Ju Ren, Qianming Yang, Mei Wen, Nan Wu, Chunyuan Zhang
2008 J jnl
On-Chip Memory System Optimization Design for the FT64 Scientific Stream Accelerator.
IEEE Micro
Mei Wen, Nan Wu, Chunyuan Zhang, Qianming Yang, Ju Ren, Yi He, Wei Wu, Jun Chai, Maolin Guan, Changqing Xun
2007 — conf
A Stream System-on-Chip Architecture for High Speed Target Recognition Based on Biologic Vision.
Asia-Pacific Computer Systems Architecture Conference
Nan Wu, Qianming Yang, Mei Wen, Yi He, Changqing Xun, Chunyuan Zhang
2007 Misc conf
FT64: Scientific Computing with Streams.
HiPC
Mei Wen, Nan Wu, Chunyuan Zhang, Wei Wu, Qianming Yang, Changqing Xun