Qianjian Xing

15 papers Journal 15
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Fast Floating-Point Multiply-Accumulator Optimized for Sparse Linear Algebra on FPGAs.
IEEE Trans. Very Large Scale Integr. Syst.
Kun Li, Xiangyu Hao, Zhenguo Ma, Feng Yu, Bo Zhang, Qianjian Xing
2025 J jnl
A Pipelined Architecture for Interatomic Interactions Computation Considering Atomic Distribution.
IEEE Access
Chengyang Han, Jifeng Luo, Yan Pei, Qianjian Xing, Feng Yu
2025 J jnl
Area-Efficient Pipeline Architecture for Serial Real-Valued Fast Fourier Transform.
IEEE Trans. Very Large Scale Integr. Syst.
Kun Li, Hongji Fang, Zhenguo Ma, Feng Yu, Bo Zhang, Qianjian Xing
2025 J jnl
Multi-Scale Contextual Coding for Human-Machine Vision of Volumetric Medical Images.
IEEE Access
Jietao Chen, Weijie Chen, Qianjian Xing, Feng Yu
2021 J jnl
High-Parallelism Hash-Merge Architecture for Accelerating Join Operation on FPGA.
IEEE Trans. Circuits Syst. II Express Briefs
Wen-Qi Wu, Meiting Xue, Qianjian Xing, Feng Yu
2020 J jnl
FPGA-Accelerated Hash Join Operation for Relational Databases.
IEEE Trans. Circuits Syst. II Express Briefs
Meiting Xue, Qianjian Xing, Chen Feng, Feng Yu, Zhen-guo Ma
2020 J jnl
HKSiamFC: Visual-Tracking Framework Using Prior Information Provided by Staple and Kalman Filter.
Sensors
Chenpu Li, Qianjian Xing, Zhenguo Ma
2020 J jnl
MFCFSiam: A Correlation-Filter-Guided Siamese Network with Multifeature for Visual Tracking.
Wirel. Commun. Mob. Comput.
Chenpu Li, Qianjian Xing, Zhenguo Ma, Ke Zang
2018 J jnl
A Fused Continuous Floating-Point MAC on FPGA.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Min Yuan, Qianjian Xing, Zhen-guo Ma, Feng Yu, Yingke Xu
2017 J jnl
A Continuous-Flow Memory-Based Architecture for Real-Valued FFT.
IEEE Trans. Circuits Syst. II Express Briefs
Xiubin Mao, Zhen-guo Ma, Feng Yu, Qianjian Xing
2017 J jnl
A Novel Conflict-Free Parallel Memory Access Scheme for FFT Processors.
IEEE Trans. Circuits Syst. II Express Briefs
Qianjian Xing, Zhen-guo Ma, Yingke Xu
2017 J jnl
A Novel Memory-Based Radix-2 Fast Walsh-Hadamard-Fourier Transform Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Qianjian Xing, Zhen-guo Ma, Feng Yu
2017 J jnl
Modular Serial Pipelined Sorting Architecture for Continuous Variable-Length Sequences with a Very Simple Control Strategy.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Tingting Chen, Weijun Li, Feng Yu, Qianjian Xing
2015 J jnl
Pipelined Architecture for a Radix-2 Fast Walsh-Hadamard-Fourier Transform Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs
Jinqi Liu, Qianjian Xing, Xiaobo Yin, Xiubin Mao, Feng Yu
2014 J jnl
Radix-R WHT-FFT with Identical Stage-to-Stage Interconnection Pattern.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Qianjian Xing, Feng Yu, Xiaobo Yin, Bei Zhao