Qiang Liu

106 papers A* 4A 6B 7C 9Misc 6Journal 49Unranked 24
YearRankTypeTitle / Venue / Authors
2026 J jnl
ALN: Approximate Layer Normalization for Transformer Training on Edge Device.
IEEE Trans. Computers
Yingchang Mao, Qiang Liu
2026 A conf
CODESCA: Co-Design for Spectral Clustering Acceleration.
FPGA
Zhengyan Liu, Ce Guo, Zehuan Zhang, Qiang Liu, Wayne Luk
2026 J jnl
Corrigendum: Unified and Efficient Factor Graph Accelerator Design for Robotic Optimization.
ACM Trans. Archit. Code Optim.
Qiang Liu, Yihao Hua, Yuhui Hao, Bo Yu, Shaoshan Liu, Yiming Gan
2026 A conf
Cost-efficient Archive Cloud Storage with Tape: Design and Deployment.
FAST
Qing Wang, Fan Yang, Qiang Liu, Geng Xiao, Yongpeng Chen, Hao Lan, Leiming Chen, Bangzhu Chen, Chenrui Liu, Pingchang Bai, Bin Huang, Zigan Luo, Mingyu Xie, Yu Wang, Youyou Lu, Huatao Wu, Jiwu Shu
2026 J jnl
HSA: An Efficient Sparse CNN Accelerator Based on Kernel-Aware Hybrid Pruning.
IEEE Trans. Very Large Scale Integr. Syst.
Xiyan Liu, Qiang Liu
2025 — conf
ACLAM: Accuracy-Configurable Logarithmic Approximate Floating-point Multiplier.
ASP-DAC
Zhongyu Guan, Qiang Liu, Guangdong Lin
2025 — conf
An Efficient Barrett Modular Multiplier Design for Zero-Knowledge Proof.
AsianHOST
Jiahao Li, Qiang Liu, Ray C. C. Cheung, Zhaohui Guo
2025 A* conf
Dadu-Corki: Algorithm-Architecture Co-Design for Embodied AI-powered Robotic Manipulation.
ISCA
Yiyang Huang, Yuhui Hao, Bo Yu, Feng Yan, Yuxin Yang, Feng Min, Yinhe Han, Lin Ma, Shaoshan Liu, Qiang Liu, Yiming Gan
2025 J jnl
Detect and Replace: Efficient Soft Error Protection of FPGA-Based CNN Accelerators.
IEEE Trans. Very Large Scale Integr. Syst.
Zhen Gao, Yanmao Qi, Jinchang Shi, Qiang Liu, Guangjun Ge, Yu Wang, Pedro Reviriego
2025 J jnl
LHAM: Low-Cost and High-Accuracy Approximate Multiplier for FPGA-Based Computing.
ACM Trans. Reconfigurable Technol. Syst.
Mingyu Shu, Qiang Liu
2025 J jnl
Robustness Against Faults in Configuration Memories of FPGA-Based LLMs.
IEEE Trans. Circuits Syst. Artif. Intell.
Zhen Gao, Lini Yuan, Jingyan Wang, Qiang Liu, Javier Conde, Pedro Reviriego, Shulin Zeng, Yu Wang, Shanshan Liu, Fabrizio Lombardi
2025 C conf
SDTA: An Efficient Sparse DNN Training Accelerator with Data Hierarchical Pre-fetching and Dynamic Scheduling.
ISCAS
Mengting Wang, Yuntao Han, Yingchang Mao, Peng Shao, Zhengyan Liu, Qiang Liu
2024 — conf
A DRAM Chip Protection Method Against EMFI Based on PHOTON Hash.
ITC-Asia
Longtao Guo, Qiang Liu
2024 C conf
A Data-Distribution Aware Approximate Multiplier Design Based on FPGA.
ISCAS
Mingyu Shu, Yingchang Mao, Qiang Liu
2024 J jnl
AQA: An Adaptive Post-Training Quantization Method for Activations of CNNs.
IEEE Trans. Computers
Yun Wang, Qiang Liu
2024 J jnl
Acceleration of Multi-Body Molecular Dynamics With Customized Parallel Dataflow.
IEEE Trans. Parallel Distributed Syst.
Quan Deng, Qiang Liu, Ming Yuan, Xiaohui Duan, Lin Gan, Jinzhe Yang, Wenlai Zhao, Zhenxiang Zhang, Guiming Wu, Wayne Luk, Haohuan Fu, Guangwen Yang
2024 J jnl
An Efficient FPGA-based Depthwise Separable Convolutional Neural Network Accelerator with Hardware Pruning.
ACM Trans. Reconfigurable Technol. Syst.
Zhengyan Liu, Qiang Liu, Shun Yan, Ray C. C. Cheung
2024 J jnl
Corki: Enabling Real-time Embodied AI Robots via Algorithm-Architecture Co-Design.
CoRR
Yiyang Huang, Yuhui Hao, Bo Yu, Feng Yan, Yuxin Yang, Feng Min, Yinhe Han, Lin Ma, Shaoshan Liu, Qiang Liu, Yiming Gan
2024 C conf
ESFLOW: Mapping Large-Scale Earthquake Simulation to Spatial Computing Systems.
ISCAS
Ming Yuan, Qiang Liu, Lin Gan, Guangwen Yang
2024 J jnl
HNMC: Hybrid Near-Memory Computing Circuit for Neural Network Acceleration.
IEEE Trans. Circuits Syst. II Express Briefs
Xiyan Liu, Qiang Liu
2024 — conf
MSCA: A Multi-Grained Sparse Convolution Accelerator for DNN Training.
ASAP
Yingchang Mao, Qiang Liu, Ray C. C. Cheung
2024 J jnl
Modeling the Effect of SEUs on the Configuration Memory of SRAM-FPGA-Based CNN Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Zhen Gao, Jiaqi Feng, Shihui Gao, Qiang Liu, Guangjun Ge, Yu Wang, Pedro Reviriego
2024 J jnl
Modular-Based Compression Scheme for Address Data in the Blockchain System for IoV Applications.
IEEE Trans. Veh. Technol.
Zhaohui Guo, Qiang Liu, Zhen Gao, Lei Liu, Yi Gong, Ximeng Liu, Neeraj Kumar, Mohsen Guizani
2024 — conf
ORIANNA: An Accelerator Generation Framework for Optimization-based Robotic Applications.
ASPLOS (2)
Yuhui Hao, Yiming Gan, Bo Yu, Qiang Liu, Yinhe Han, Zishen Wan, Shaoshan Liu
2024 C conf
PBN: Progressive Batch Normalization for DNN Training on Edge Device.
ISCAS
Yingchang Mao, Mingyu Shu, Qiang Liu
2024 J jnl
Verkle-Accumulator-Based Stateless Transaction Validation (VA-STV) Scheme for the Blockchain-Based IoT Network.
IEEE Internet Things J.
Zhaohui Guo, Zhen Gao, Qiang Liu, Lei Liu, Mianxiong Dong, Ning Zhang, Mohammed Atiquzzaman
2023 J jnl
A Methodology for the Design of Fault Tolerant Parallel Digital Channelizers on SRAM-FPGAs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhen Gao, Jiajun Xiao, Qiang Liu, Anees Ullah, Pedro Reviriego
2023 C conf
A Portable DSP Coprocessor Design Using RISC-V Packed-SIMD Instructions.
ISCAS
Kai Li, Wei Yin, Qiang Liu
2023 C conf
An Adaptive Quantization Method for CNN Activations.
ISCAS
Yun Wang, Qiang Liu
2023 J jnl
An Energy Efficient and Runtime Reconfigurable Accelerator for Robotic Localization.
IEEE Trans. Computers
Qiang Liu, Yuhui Hao, Weizhuang Liu, Bo Yu, Yiming Gan, Jie Tang, Shaoshan Liu, Yuhao Zhu
2023 — conf
An FPGA-based Mix-grained Sparse Training Accelerator.
ICFPT
Yingchang Mao, Qiang Liu
2023 A* conf
BLITZCRANK: Factor Graph Accelerator for Motion Planning.
DAC
Yuhui Hao, Yiming Gan, Bo Yu, Qiang Liu, Shaoshan Liu, Yuhao Zhu
2023 J jnl
Efficient Protection of FPGA Implemented LDPC Decoders Against Single Event Upsets (SEUs) on Configuration Memories.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhen Gao, Yinghao Cheng, Qiang Liu, Anees Ullah, Pedro Reviriego
2023 J jnl
FGLQR: Factor Graph Accelerator of LQR Control for Autonomous Machines.
CoRR
Yuhui Hao, Bo Yu, Qiang Liu, Shaoshan Liu
2023 A conf
Fault Model Analysis of DRAM under Electromagnetic Fault Injection Attack.
DATE
Qiang Liu, Longtao Guo, Honghui Tang
2023 J jnl
Guest Editorial Special Issue on the Asian Hardware Oriented Security and Trust Symposium (AsianHOST 2022).
IEEE Trans. Circuits Syst. I Regul. Pap.
Chip-Hong Chang, Pingqiang Zhou, Yuan Cao, Qiang Liu
2023 J jnl
Introduction to Special Section on FPT'20.
ACM Trans. Reconfigurable Technol. Syst.
Oliver Sinnen, Qiang Liu, Azadeh Davoodi
2023 J jnl
Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders.
IEEE Trans. Very Large Scale Integr. Syst.
Zhen Gao, Jinchang Shi, Qiang Liu, Anees Ullah, Pedro Reviriego
2022 — conf
An Energy-Efficient and Runtime-Reconfigurable FPGA-Based Accelerator for Robotic Localization Systems.
CICC
Qiang Liu, Zishen Wan, Bo Yu, Weizhuang Liu, Shaoshan Liu, Arijit Raychowdhury
2022 J jnl
An Energy-Efficient and Runtime-Reconfigurable FPGA-Based Accelerator for Robotic Localization Systems.
CoRR
Qiang Liu, Zishen Wan, Bo Yu, Weizhuang Liu, Shaoshan Liu, Arijit Raychowdhury
2022 Misc conf
DQI: A Dynamic Quantization Method for Efficient Convolutional Neural Network Inference Accelerators.
FCCM
Yun Wang, Qiang Liu, Shun Yan
2022 — conf
FPGA-Accelerated Tersoff Multi-body Potential for Molecular Dynamics Simulations.
ARC
Ming Yuan, Qiang Liu, Quan Deng, Shengye Xiang, Lin Gan, Jinzhe Yang, Xiaohui Duan, Haohuan Fu, Guangwen Yang
2022 A conf
Factor Graph Accelerator for LiDAR-Inertial Odometry (Invited Paper).
ICCAD
Yuhui Hao, Bo Yu, Qiang Liu, Shaoshan Liu, Yuhao Zhu
2022 J jnl
Factor Graph Accelerator for LiDAR-Inertial Odometry.
CoRR
Yuhui Hao, Bo Yu, Qiang Liu, Shaoshan Liu, Yuhao Zhu
2022 J jnl
Fault Injection Attack Emulation Framework for Early Evaluation of IC Designs.
ACM Trans. Design Autom. Electr. Syst.
Qiang Liu, Honghui Tang, Peiran Zhang
2022 — conf
In-depth Analysis of the Effects of Electromagnetic Fault Injection Attack on a 32-bit MCU.
SOCC
Jinteng Jiao, He Li, Yanzhao Feng, Chengdong Qian, Qiang Liu
2022 — conf
LCAM: Low-Cost Approximate Multiplier Design on FPGA.
FPT
Mingyu Shu, Qiang Liu
2022 J jnl
MPFA: An Efficient Multiple Faults-Based Persistent Fault Analysis Method for Low-Cost FIA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Honghui Tang, Qiang Liu
2022 J jnl
RNS-Based Adaptive Compression Scheme for the Block Data in the Blockchain for IIoT.
IEEE Trans. Ind. Informatics
Zhaohui Guo, Zhen Gao, Qiang Liu, Chinmay Chakraborty, Qiaozhi Hua, Keping Yu, Shaohua Wan
2021 C conf
A Digital and Lightweight Delay-Based Detector against Fault Injection Attacks.
ISCAS
Maoshen Zhang, Qiang Liu
2021 J jnl
Adversarial Hardware With Functional and Topological Camouflage.
IEEE Trans. Circuits Syst. II Express Briefs
He Li, Ameer Abdelhadi, Runbin Shi, Jiliang Zhang, Qiang Liu
2021 B conf
An FPGA-based MobileNet Accelerator Considering Network Structure Characteristics.
FPL
Shun Yan, Zhengyan Liu, Yun Wang, Chenglong Zeng, Qiang Liu, Bowen Cheng, Ray C. C. Cheung
2021 A* conf
Archytas: A Framework for Synthesizing and Dynamically Optimizing Accelerators for Robotic Localization.
MICRO
Weizhuang Liu, Bo Yu, Yiming Gan, Qiang Liu, Jie Tang, Shaoshan Liu, Yuhao Zhu
2021 A* conf
Eudoxus: Characterizing and Accelerating Localization in Autonomous Machines Industry Track Paper.
HPCA
Yiming Gan, Bo Yu, Boyuan Tian, Leimeng Xu, Wei Hu, Shaoshan Liu, Qiang Liu, Yanjun Zhang, Jie Tang, Yuhao Zhu
2021 — conf
Experimental Verification of EMPA Fault Mechanism.
NANOARCH
Maoshen Zhang, Qiang Liu
2021 C conf
Lightweight and Configurable Synchronizer and Demodulator Design for PDSCH on FPGA.
ISCAS
Chongguang Yao, Qiang Liu, Linan Wang, Qingye Zhang, Honghui Tang, Maoshen Zhang
2020 J jnl
$\pi$π-BA: Bundle Adjustment Hardware Accelerator Based on Distribution of 3D-Point Observations.
IEEE Trans. Computers
Qiang Liu, Shuzhen Qin, Bo Yu, Jie Tang, Shaoshan Liu
2020 J jnl
Eudoxus: Characterizing and Accelerating Localization in Autonomous Machines.
CoRR
Yiming Gan, Yu Bo, Boyuan Tian, Leimeng Xu, Wei Hu, Shaoshan Liu, Qiang Liu, Yanjun Zhang, Jie Tang, Yuhao Zhu
2020 J jnl
Peak Detection Based on FPGA Using Quasi-Newton Optimization Method for Femtosecond Laser Ranging.
IEEE Access
Yu Jiang, Qiang Liu, Hui Cao, Youjian Song
2019 J jnl
A Hardware Trojan Detection Method Based on Structural Features of Trojan and Host Circuits.
IEEE Access
Qiang Liu, Pengyong Zhao, Fuqiang Chen
2019 — conf
Density-based Clustering Method for Hardware Trojan Detection Based on Gate-level Structural Features.
AsianHOST
Pengyong Zhao, Qiang Liu
2019 J jnl
Heterogeneous Acceleration of Hybrid PSO-QN Algorithm for Neural Network Training.
IEEE Access
Shun Yan, Qiang Liu, Jiajun Li, Liang Han
2019 J jnl
Information Theory-Based Quantitative Evaluation Method for Countermeasures Against Fault Injection Attacks.
IEEE Access
Qiang Liu, Bo Ning, Pengjie Deng
2019 J jnl
PI-BA Bundle Adjustment Acceleration on Embedded FPGAs with Co-observation Optimization.
CoRR
Shuzhen Qin, Qiang Liu, Bo Yu, Shaoshan Liu
2019 Misc conf
π-BA: Bundle Adjustment Acceleration on Embedded FPGAs with Co-observation Optimization.
FCCM
Shuzhen Qin, Qiang Liu, Bo Yu, Shaoshan Liu
2018 J jnl
A Low Cost Partial Scan Approach Based on Balanced Sequential Graph Transformation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tao Li, Qiang Liu
2018 J jnl
Fast Neural Network Training on FPGA Using Quasi-Newton Optimization Method.
IEEE Trans. Very Large Scale Integr. Syst.
Qiang Liu, Jia Liu, Ruoyu Sang, Jiajun Li, Tao Zhang, Qijun Zhang
2018 J jnl
Signal word-level statistical properties-based activation approach for hardware Trojan detection in DSP circuits.
IET Comput. Digit. Tech.
He Li, Qiang Liu, Fuqiang Chen
2017 B conf
F-C3D: FPGA-based 3-dimensional convolutional neural network.
FPL
Hongxiang Fan, Xinyu Niu, Qiang Liu, Wayne Luk
2017 — conf
Neural Network Training Acceleration with PSO Algorithm on a GPU Using OpenCL.
HEART
Jiajun Li, Qiang Liu
2017 — conf
Optimizing CNN-Based Object Detection Algorithms on Embedded FPGA Platforms.
ARC
Ruizhe Zhao, Xinyu Niu, Yajie Wu, Wayne Luk, Qiang Liu
2016 J jnl
A survey of hardware Trojan threat and defense.
Integr.
He Li, Qiang Liu, Jiliang Zhang
2016 J jnl
Accuracy Improvement of Energy Prediction for Solar-Energy-Powered Embedded Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Qiang Liu, Qijun Zhang
2016 Misc conf
Cost Effective Partial Scan for Hardware Emulation.
FCCM
Tao Li, Qiang Liu
2016 — conf
IC security evaluation against fault injection attack based on FPGA emulation.
FPT
Song Xu, Qiang Liu, Tao Li, Hongxiang Fan
2016 J jnl
IP Protection of Mesh NoCs Using Square Spiral Routing.
IEEE Trans. Very Large Scale Integr. Syst.
Qiang Liu, Wenqing Ji, Qi Chen, Terrence S. T. Mak
2016 J jnl
Knowledge-Based Neural Network Model for FPGA Logical Architecture Development.
IEEE Trans. Very Large Scale Integr. Syst.
Qiang Liu, Ming Gao, Qijun Zhang
2015 — conf
A Survey of Hardware Trojan Detection, Diagnosis and Prevention.
CAD/Graphics
He Li, Qiang Liu, Jiliang Zhang, Yongqiang Lyu
2015 J jnl
Automating Elimination of Idle Functions by Runtime Reconfiguration.
ACM Trans. Reconfigurable Technol. Syst.
Xinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu, Oliver Pell
2015 B conf
Pipelined NoC router architecture design with buffer configuration exploration on FPGA.
FPL
Qi Chen, Qiang Liu
2015 J jnl
Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Qiang Liu, Terrence S. T. Mak, Tao Zhang, Xinyu Niu, Wayne Luk, Alex Yakovlev
2014 J jnl
Comments on "Algorithmic Aspects of Hardware/Software Partitioning: 1D Search Algorithms".
IEEE Trans. Computers
Hao-Jun Quan, Tao Zhang, Qiang Liu, Jichang Guo, Xiaochen Wang, Ruimin Hu
2014 — conf
Hardware Trojan detection acceleration based on word-level statistical properties management.
FPT
He Li, Qiang Liu
2013 Misc conf
Automating Elimination of Idle Functions by Run-Time Reconfiguration.
FCCM
Xinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu
2013 A conf
Automating resource optimisation in reconfigurable design (abstract only).
FPGA
Xinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu
2012 J jnl
Automated Mapping of the MapReduce Pattern onto Parallel Computing Platforms.
J. Signal Process. Syst.
Qiang Liu, Tim Todman, Wayne Luk, George A. Constantinides
2012 B conf
Exploiting run-time reconfiguration in stencil computation.
FPL
Xinyu Niu, Qiwei Jin, Wayne Luk, Qiang Liu, Oliver Pell
2012 — conf
Heterogeneous Systems for Energy Efficient Scientific Computing.
ARC
Qiang Liu, Wayne Luk
2012 — conf
Neural network based pre-placement wirelength estimation.
FPT
Qiang Liu, Jianguo Ma, Qijun Zhang
2012 J jnl
Optimizing Hardware Design by Composing Utility-Directed Transformations.
IEEE Trans. Computers
Qiang Liu, Tim Todman, Wayne Luk, George A. Constantinides
2011 J jnl
Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organization.
Comput. J.
Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung
2011 — conf
Objective-driven workload allocation in heterogeneous computing systems.
FPT
Qiang Liu, Wayne Luk
2011 — conf
Power adaptive computing system design in energy harvesting environment.
ICSAMOS
Qiang Liu, Terrence S. T. Mak, Junwen Luo, Wayne Luk, Alexandre Yakovlev
2010 Misc conf
A Scripting Engine for Combining Design Transformations.
FCCM
Tim Todman, Qiang Liu, Wayne Luk, George A. Constantinides
2010 A conf
Combining optimizations in automated low power design.
DATE
Qiang Liu, Tim Todman, Wayne Luk
2010 — conf
Convex models for accelerating applications on FPGA-based clusters.
FPT
Qiang Liu, Tim Todman, Kuen Hung Tsoi, Wayne Luk
2010 C conf
Customizable Composition and Parameterization of Hardware Design Transformations.
DSD
Tim Todman, Qiang Liu, Wayne Luk, George A. Constantinides
2009 — conf
A high-level compilation toolchain for heterogeneous systems.
SoCC
Wayne Luk, José Gabriel de Figueiredo Coutinho, Timothy John Todman, Yuet Ming Lam, William George Osborne, Kong Woei Susanto, Qiang Liu, W. S. Wong
2009 J jnl
Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung
2009 J jnl
Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems.
IET Comput. Digit. Tech.
Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung
2009 B conf
Optimising designs by combining model-based and pattern-based transformations.
FPL
Qiang Liu, Tim Todman, José Gabriel de Figueiredo Coutinho, Wayne Luk, George A. Constantinides
2008 B conf
Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework.
FPL
Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung
2008 — conf
Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation.
BCS Int. Acad. Conf.
Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung
2008 — —
Data Reuse and Parallelism in Hardware Compilation.
Qiang Liu
2007 Misc conf
Automatic On-chip Memory Minimization for Data Reuse.
FCCM
Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung
2006 B conf
Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm.
FPL
Konstantinos Masselos, George A. Constantinides, Qiang Liu