Qiang Li - RankMe

112 papers C 23Misc 1Journal 44Unranked 44

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	An 8-bit Precision 10T SRAM Compute-in-Memory Macro Using ADC With Small Area. IEEE Trans. Circuits Syst. II Express Briefs Tianyu Chen, Haoyu Zhuang, Yajuan He, Qiang Li
2025	J	`jnl`	A 0.69-Noise-Efficiency-Factor 55× -Preamp-Gain Dynamic Comparator With a Stacking FIA. IEEE J. Solid State Circuits Haoyu Zhuang, Yirui Cao, Linzhi Tao, Qiang Li
2025	J	`jnl`	A Chopping-Free Single-Trim Bandgap Reference Using Amplifier With PTAT Offset. IEEE J. Solid State Circuits Haoyu Zhuang, Yuntao Cao, Shuguang Han, Siyuan Liu, Yizhan Li, Rongqing Sheng, Qiang Li
2025	J	`jnl`	A High-Accuracy Bandgap Reference With Compact Output Driver. IEEE Trans. Circuits Syst. II Express Briefs Haoyu Zhuang, Yizhan Li, Xingyu Wang, Liangchen Huang, Qiang Li
2025	—	`conf`	A Timing-Robust 10b 13GS/s ADC with Analog Fourier Transform Based Frequency Interleaving. CICC Xingchen Chao, Yunqiang Xu, Qiang Yu, Zheng Zhu, Sanfeng Zhang, Qiang Li
2025	J	`jnl`	Graph-Based Joint Client Clustering and Resource Allocation for Wireless Distributed Learning: A New Hierarchical Federated Learning Framework With Non-IID Data. IEEE Trans. Mob. Comput. Ercong Yu, Shanyun Liu, Qiang Li, Hongyang Chen, H. Vincent Poor, Shlomo Shamai
2024	—	`conf`	131TOPS/W 8b ACIM Exploiting Weight-Embedded Auto-Accumulation and Supporting Symmetric Quantization Networks. CICC Wei He, Puvi Bai, Hongyang Luo, Zhenghao Jin, Han Wu, Junyi Zhang, Xingchen Chao, Haiqi Liu, Yajuan He, Qiang Li
2024	J	`jnl`	A 0.5-V Voltage Reference Using Simple Common-Source Amplifier With Improved Gain. IEEE Trans. Circuits Syst. II Express Briefs Haoyu Zhuang, Qiang Li
2024	J	`jnl`	A 0.8-V Supply, 1.58% 3σ-Accuracy, 1.9-μW Bandgap Reference in 0.13-μm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Yirui Cao, Haoyu Zhuang, Qiang Li
2024	J	`jnl`	A 20 MHz, 98.7 dB-SFDR, Capacitively Degenerated Dynamic Amplifier Without Bias Voltage Calibrations. IEEE Trans. Circuits Syst. II Express Briefs Ruofan Zhang, Haoyu Zhuang, Yirui Cao, Qiang Li
2024	J	`jnl`	A Compact Sub-nW/kHz Relaxation Oscillator Using a Negative-Offset Comparator With Chopping and Piecewise Charge-Acceleration in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Yueduo Liu, Zihao Zhu, Rongxin Bao, Jiahui Lin, Jun Yin, Qiang Li, Pui-In Mak, Shiheng Yang
2024	J	`jnl`	A low power 16-bit 50 MS/s pipeline ADC with 104 dB SFDR in 0.18 μm CMOS. Microelectron. J. Xiaodan Zhou, Weipeng He, Dongbing Fu, Jianan Wang, Guangbing Chen, Qiang Li
2024	J	`jnl`	Deep Learning Assisted Multiuser MIMO Load Modulated Systems for Enhanced Downlink mmWave Communications. IEEE Trans. Wirel. Commun. Ercong Yu, Jinle Zhu, Qiang Li, Zi Long Liu, Hongyang Chen, Shlomo Shamai Shitz, H. Vincent Poor
2023	J	`jnl`	A 0.0043-mm IEEE Trans. Very Large Scale Integr. Syst. Yuchen Wei, Shiheng Yang, Yueduo Liu, Rongxin Bao, Zihao Zhu, Jiahui Lin, Zehao Zhang, Yong Chen, Jun Yin, Pui-In Mak, Qiang Li
2023	—	`conf`	A 0.69-Noise-Efficiency-Factor 4 x-Current-Reuse Dynamic Comparator with A Stacking FIA. CICC Haoyu Zhuang, Nan Sun, Yirui Cao, Linzhi Tao, Qiang Li
2023	C	`conf`	A 128-GS/s Timing-Robust Sampling Architecture Exploiting Analog FFT. ISCAS Xingchen Chao, Qiang Li
2023	C	`conf`	A Low-Noise and Settling-Enhanced Switched-Capacitor Amplifier With Correlated Level Shifting and Bandwidth Switching. ISCAS Feng Tai, Ziqin Nie, Yinhao Wang, Xingchen Chao, Qiang Li
2023	—	`conf`	Bitwise ELD Compensation under Integrator Nonidealities in ΔΣ Modulators. NEWCAS Michael Pietzko, Julian Spiess, Jonathan Ungethüm, John G. Kauffman, Qiang Li, Maurits Ortmanns
2023	—	`conf`	Improved Dynamic Comparator With Adaptive Delay Line for the Latch Conduction and Regenerative Feedback Assisted FIA. NEWCAS Feng Tai, Qiang Li
2023	J	`jnl`	On the DC-Settling Process of the Pierce Crystal Oscillator in Start-Up. IEEE Trans. Circuits Syst. II Express Briefs Zehao Zhang, Shiheng Yang, Yueduo Liu, Zihao Zhu, Jiahui Lin, Rongxin Bao, Tailong Xu, Zhizhan Yang, Mingkang Zhang, Jiaxin Liu, Xiong Zhou, Jun Yin, Pui-In Mak, Qiang Li
2023	J	`jnl`	TT@CIM: A Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity Optimization and Variable Precision Quantization. IEEE J. Solid State Circuits Ruiqi Guo, Zhiheng Yue, Xin Si, Hao Li, Te Hu, Limei Tang, Yabing Wang, Hao Sun, Leibo Liu, Meng-Fan Chang, Qiang Li, Shaojun Wei, Shouyi Yin
2022	—	`conf`	16- and 64-Point Analog Computing of FFT with Improved Performance and Efficiency. PRIME Jingjing Li, Xingchen Chao, Qiang Li
2022	C	`conf`	A 100dB-TCMRR 8-Channel Bio-Potential Front-End with Multi-Channel Common-Mode Replication. ISCAS Borui Tan, Sanfeng Zhang, Chen Gao, Xiong Zhou, Qiang Li
2022	C	`conf`	A 13-bit 1-MS/s SAR ADC With Rotation-Based Mismatch Error Cancellation. ISCAS Jing Zhang, Lulu Zhang, Xiong Zhou, Maurits Ortmanns, Qiang Li
2022	J	`jnl`	A 130-dB CMRR Instrumentation Amplifier With Common-Mode Replication. IEEE J. Solid State Circuits Sanfeng Zhang, Xiong Zhou, Chen Gao, Qiang Li
2022	—	`conf`	A 4.2-to-5.6 GHz Transformer-Based PMOS-only Stacked-gm VCO in 28-nm CMOS. ICTA Mingkang Zhang, Zihao Zhu, Yueduo Liu, Zehao Zhang, Rongxin Bao, Jiahui Lin, Haovu Zhuang, Jiaxin Liu, Xiong Zhou, Shiheng Yang, Qiang Li
2022	J	`jnl`	Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop. IEEE Trans. Circuits Syst. I Regul. Pap. Yueduo Liu, Rongxin Bao, Zihao Zhu, Shiheng Yang, Xiong Zhou, Jun Yin, Pui-In Mak, Qiang Li
2022	J	`jnl`	An On-Chip Power-Supply Noise Analyzer With Compressed Sensing and Enhanced Quantization. IEEE J. Solid State Circuits Pengfei Zhai, Zheng Zhu, Xiong Zhou, Yan Cai, Fan Zhang, Qiang Li
2022	C	`conf`	Bitwise ELD Compensation in Δ∑ Modulators. ISCAS Michael Pietzko, Jonathan Ungethüm, John G. Kauffman, Qiang Li, Maurits Ortmanns
2022	C	`conf`	Maximizing the Inter-Stage Gain in CT 0-X MASH Delta-Sigma-Modulators. ISCAS Jonathan Ungethüm, Michael Pietzko, John G. Kauffman, Qiang Li, Maurits Ortmanns
2021	—	`conf`	15.4 A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization. ISSCC Ruiqi Guo, Zhiheng Yue, Xin Si, Te Hu, Hao Li, Limei Tang, Yabing Wang, Leibo Liu, Meng-Fan Chang, Qiang Li, Shaojun Wei, Shouyi Yin
2021	C	`conf`	A 40nm 1Mb 35.6 TOPS/W MLC NOR-Flash Based Computation-in-Memory Structure for Machine Learning. ISCAS Yuxin Zhang, Sitao Zeng, Zhiguo Zhu, Zhaolong Qin, Chen Wang, Jingjing Li, Sanfeng Zhang, Yajuan He, Chunmeng Dou, Xin Si, Meng-Fan Chang, Qiang Li
2021	J	`jnl`	A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Shiheng Yang, Jun Yin, Tailong Xu, Taimo Yi, Pui-In Mak, Qiang Li, Rui Paulo Martins
2021	—	`conf`	A 640×512 30μm Pixel Pitch 1.8mK-NETD 90.1dB-SNR Digital Read-out Integrated Circuit with Fully On-chip Image Algorithm Pixel-Level Calibration. A-SSCC Yan Zeng, Shiheng Yang, Yueduo Liu, Zehao Li, Wengang Huang, Xiaozong Huang, Xiong Zhou, Jiaxin Liu, Qiang Li
2021	—	`conf`	A 9.08 ENOB 10b 400MS/s Subranging SAR ADC with Subsetted CDAC and PDAS in 40nm CMOS. ESSCIRC Qiang Yu, Xiong Zhou, Kefeng Hu, Zijian Huang, Haiwen Chen, Xin Si, Jinda Yang, Qiang Li
2021	—	`conf`	A Comparator Speed Enhancement Technique for Near- and Sub-Threshold ADCs. ICECS Bojun Hu, Sanfeng Zhang, Xiong Zhou, Zehao Li, Xiangxin Pan, Zhaoming Ding, Qiang Li
2021	C	`conf`	A Ku-Band SiGe Phased-Array Transceiver with 6-Bit Phase and Attenuation Control. ISCAS Bojun Hu, Chao Liu, Sanfeng Zhang, Qiang Li
2021	J	`jnl`	A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips. IEEE J. Solid State Circuits Xin Si, Yung-Ning Tu, Wei-Hsing Huang, Jian-Wei Su, Pei-Jung Lu, Jing-Hong Wang, Ta-Wei Liu, Ssu-Yen Wu, Ruhui Liu, Yen-Chi Chou, Yen-Lin Chung, William Shih, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Nan-Chun Lien, Wei-Chiang Shih, Yajuan He, Qiang Li, Meng-Fan Chang
2021	—	`conf`	A Low Power Sample-and-Hold Circuit with Improved Dynamic Bias for Pipelined ADC. APCCAS Xiaodan Zhou, Zehao Li, Yujie Wang, Xiong Zhou, Shiheng Yang, Jiaxin Liu, Qiang Li
2021	—	`conf`	A Low-Power RC Oscillator with Offset and Path Delay Cancellation. ICTA Yueduo Liu, Zihao Zhu, Rongxin Bao, Shiheng Yang, Jiaxin Liu, Xiong Zhou, Qiang Li
2021	C	`conf`	A Sampling Speed Enhancement Technique for Near-Threshold SAR ADCs. ISCAS Bojun Hu, Sanfeng Zhang, Xiong Zhou, Xiangxin Pan, Zhaoming Ding, Qiang Li
2021	J	`jnl`	An AC-Coupled Instrumentation Amplifier Achieving 110-dB CMRR at 50 Hz With Chopped Pseudoresistors and Successive-Approximation-Based Capacitor Trimming. IEEE J. Solid State Circuits Sanfeng Zhang, Xiong Zhou, Chen Gao, Qiang Li
2021	J	`jnl`	ECDR$^{2}$2: Error Corrector and Detector Relocation Router for Network-on-Chip. IEEE Trans. Computers Letian Huang, Chikun Yuan, Junshi Wang, Masoumeh Ebrahimi, Xuan Xie, Qiang Li
2021	J	`jnl`	Sampling and Comparator Speed-Enhancement Techniques for Near-Threshold SAR ADCs. IEEE Open J. Circuits Syst. Bojun Hu, Sanfeng Zhang, Xiangxin Pan, Xiangyu Zhao, Zhaoming Ding, Xiong Zhou, Shiheng Yang, Qiang Li
2021	—	`conf`	Teaching Logic and Sequential Cell Characterization in Digital Integrated Circuits. ICETT Yajuan He, Ziji Zhang, Xiong Zhou, Qiang Li
2020	—	`conf`	15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips. ISSCC Xin Si, Yung-Ning Tu, Wei-Hsing Huang, Jian-Wei Su, Pei-Jung Lu, Jing-Hong Wang, Ta-Wei Liu, Ssu-Yen Wu, Ruhui Liu, Yen-Chi Chou, Zhixiao Zhang, Syuan-Hao Sie, Wei-Chen Wei, Yun-Chen Lo, Tai-Hsing Wen, Tzu-Hsiang Hsu, Yen-Kai Chen, William Shih, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Nan-Chun Lien, Wei-Chiang Shih, Yajuan He, Qiang Li, Meng-Fan Chang
2020	—	`conf`	23.7 A 130dB CMRR Instrumentation Amplifier with Common-Mode Replication. ISSCC Sanfeng Zhang, Chen Gao, Xiong Zhou, Qiang Li
2020	—	`conf`	25.4 A Scalable 20GHz On-Die Power-Supply Noise Analyzer with Compressed Sensing. ISSCC Pengfei Zhai, Xiong Zhou, Yan Cai, Zheng Zhu, Fan Zhang, Qiang Li
2020	J	`jnl`	A 14-bit 4-MS/s VCO-Based SAR ADC With Deep Metastability Facilitated Mismatch Calibration. IEEE J. Solid State Circuits Zheng Zhu, Xiong Zhou, Yuheng Du, Yao Feng, Qiang Li
2020	J	`jnl`	A Fully Integrated LDO With 50-mV Dropout for Power Efficiency Optimization. IEEE Trans. Circuits Syst. II Express Briefs Xiaofei Ma, Yan Lu, Qiang Li
2020	J	`jnl`	A Probabilistic Prediction-Based Fixed-Width Booth Multiplier for Approximate Computing. IEEE Trans. Circuits Syst. Yajuan He, Xilin Yi, Ziji Zhang, Bin Ma, Qiang Li
2020	J	`jnl`	A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors. IEEE J. Solid State Circuits Xin Si, Rui Liu, Shimeng Yu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Qiang Li, Meng-Fan Chang, Jia-Jing Chen, Yung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Yen-Cheng Chiu, Wei-Chen Wei, Ssu-Yen Wu, Xiaoyu Sun
2020	J	`jnl`	An NMOS Digital LDO With NAND-Based Analog-Assisted Loop in 28-nm CMOS. IEEE Trans. Circuits Syst. Xiaofei Ma, Yan Lu, Qiang Li, Wing-Hung Ki, Rui Paulo Martins
2019	J	`jnl`	A 0.5-1.1-V Adaptive Bypassing SAR ADC Utilizing the Oscillation-Cycle Information of a VCO-Based Comparator. IEEE J. Solid State Circuits Zhaoming Ding, Xiong Zhou, Qiang Li
2019	C	`conf`	A 12-bit 30MS/s SAR ADC with VCO-Based Comparator and Split-and-Recombination Redundancy for Bypass Logic. ISCAS Sheng Chang, Xiong Zhou, Zhaoming Ding, Qiang Li
2019	J	`jnl`	A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors. IEEE Trans. Circuits Syst. I Regul. Pap. Xin Si, Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xiaoyu Sun, Rui Liu, Shimeng Yu, Hiroyuki Yamauchi, Qiang Li, Meng-Fan Chang
2019	C	`conf`	A Loss-Compensated 5-Bit Ka-Band Digital Phase Shifter with Low RMS Phase/Gain Error Over Wide Temperature Ranges. ISCAS Ruoman Yang, Chao Liu, Xiangyu Zhao, Sheng Chang, Xiong Zhou, Qiang Li
2019	—	`conf`	A Multi-Slice VCO-based Quantizer for On-Chip Power Supply Noise Analysis Achieving 0.11 (mV) A-SSCC Pengfei Zhai, Xiong Zhou, Yan Cai, Zheng Zhu, Fan Zhang, Zixiao Lin, Qiang Li
2019	—	`conf`	A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning. ISSCC Xin Si, Jia-Jing Chen, Yung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Yen-Cheng Chiu, Wei-Chen Wei, Ssu-Yen Wu, Xiaoyu Sun, Rui Liu, Shimeng Yu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Qiang Li, Meng-Fan Chang
2019	J	`jnl`	Efficient Design-for-Test Approach for Networks-on-Chip. IEEE Trans. Computers Junshi Wang, Masoumeh Ebrahimi, Letian Huang, Xuan Xie, Qiang Li, Guangjun Li, Axel Jantsch
2019	J	`jnl`	Inverter-Based Subthreshold Amplifier Techniques and Their Application in 0.3-V $\Delta\Sigma$ -Modulators. IEEE J. Solid State Circuits Lishan Lv, Xiong Zhou, Zhiliang Qiao, Qiang Li
2019	C	`conf`	Online Path-Based Test Method for Network-on-Chip. ISCAS Junkai Zhan, Letian Huang, Junshi Wang, Masoumeh Ebrahimi, Qiang Li
2018	J	`jnl`	A 0.4-V G IEEE J. Solid State Circuits Lishan Lv, Ankesh Jain, Xiong Zhou, Joachim Becker, Qiang Li, Maurits Ortmanns
2018	—	`conf`	A 0.4V 430nA quiescent current NMOS digital LDO with NAND-based analog-assisted loop in 28nm CMOS. ISSCC Xiaofei Ma, Yan Lu, Rui Paulo Martins, Qiang Li
2018	—	`conf`	A 0.5-1.1V 10B Adaptive Bypassing SAR ADC Utilizing Oscillation Cycle Information of VCO-Based Comparator. VLSI Circuits Zhaoming Ding, Xiong Zhou, Qiang Li
2018	—	`conf`	A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors. ISSCC Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xin Si, En-Yu Yang, Xiaoyu Sun, Rui Liu, Pai-Yu Chen, Qiang Li, Shimeng Yu, Meng-Fan Chang
2018	—	`conf`	A >3GHz ERBW 1.1GS/S 8B Two-Sten SAR ADC with Recursive-Weight DAC. VLSI Circuits Haiwen Chen, Xiong Zhot, Qiang Yu, Fan Zhang, Qiang Li
2018	—	`conf`	A Voltage Swing Robust Pseudo-Resistor Structure for Biomedical Front-end Amplifier. APCCAS Sanfeng Zhang, Xiong Zhou, Qiang Li
2018	—	`conf`	A lifetime-aware mapping algorithm to extend MTTF of Networks-on-Chip. ASP-DAC Letian Huang, Shuyu Chen, Qiong Wu, Masoumeh Ebrahimi, Junshi Wang, Shuyan Jiang, Qiang Li
2018	C	`conf`	An Energy-Efficient Approximate DCT for Wireless Capsule Endoscopy Application. ISCAS Yan Xing, Ziji Zhang, Yiduan Qian, Qiang Li, Yajuan He
2018	C	`conf`	Delta-Measurement Low-Power SAR ADC Architecture with Adaptive Threshold-First Switching. ISCAS Zhaoming Ding, Xiong Zhou, Qiang Li
2018	C	`conf`	Micro-Architecture Design for Low Overhead Fault Tolerant Network-on-Chip. ISCAS Chikun Yuan, Letian Huang, Junshi Wang, Qiang Li
2018	C	`conf`	Optimal Slope Ranking: An Approximate Computing Approach for Circuit Pruning. ISCAS Ziji Zhang, Yajuan He, Jin He, Xilin Yi, Qiang Li, Bo Zhang
2018	—	`conf`	Optimizing dynamic mapping techniques for on-line NoC test. ASP-DAC Shuyan Jiang, Qiong Wu, Shuyu Chen, Junshi Wang, Masoumeh Ebrahimi, Letian Huang, Qiang Li
2017	C	`conf`	A low latency fault tolerant transmission mechanism for Network-on-Chip. ISCAS Letian Huang, Xinxin Lin, Junshi Wang, Qiang Li
2017	J	`jnl`	Minimizing the system impact of router faults by means of reconfiguration and adaptive routing. Microprocess. Microsystems Junshi Wang, Masoumeh Ebrahimi, Letian Huang, Qiang Li, Guangjun Li, Axel Jantsch
2017	C	`conf`	Non-blocking BIST for continuous reliability monitoring of Networks-on-Chip. ISCAS Junshi Wang, Letian Huang, Masoumeh Ebrahimi, Qiang Li, Guangjun Li, Axel Jantsch
2017	—	`conf`	Optimization of the amplifier's input-referred noise for high resolution comparators. ASICON Qichao He, Xiong Zhou, Qiang Li
2016	—	`conf`	A wearable ear-EEG recording system based on dry-contact active electrodes. VLSI Circuits Xiong Zhou, Qiang Li, Soren Kilsgaard, Farshad Moradi, Simon Lind Kappel, Preben Kidmose
2016	J	`jnl`	An Amplifier-Free Pipeline-SAR ADC Architecture With Enhanced Speed and Energy Efficiency. IEEE Trans. Circuits Syst. II Express Briefs Junfeng Gao, Guangjun Li, Letian Huang, Qiang Li
2016	—	`conf`	Fast-settling technique under large electrode offset in integrated biopotential amplifiers. BioCAS Hailiang Yao, Xiong Zhou, Sanfeng Zhang, Qiang Li
2016	Misc	`conf`	Optimizing the location of ECC protection in network-on-chip. CODES+ISSS Junshi Wang, Letian Huang, Qiang Li, Guangjun Li, Axel Jantsch
2016	J	`jnl`	Phase-error cancellation technique for fast-lock phase-locked loop. IET Circuits Devices Syst. Zhaoming Ding, Haiqi Liu, Qiang Li
2016	—	`conf`	VisualNoC: A Visualization and Evaluation Environment for Simulation and Mapping. MES@ISCA Junshi Wang, Yang Huang, Masoumeh Ebrahimi, Letian Huang, Qiang Li, Axel Jantsch, Guangjun Li
2015	C	`conf`	300mV 50kHz 75.9dB SNDR CT ΔΣ Modulator with Inverter-based Feedforward OTAs. ISCAS Lishan Lv, Qiang Li
2015	J	`jnl`	A High-Speed Energy-Efficient Segmented Prequantize and Bypass DAC for SAR ADCs. IEEE Trans. Circuits Syst. II Express Briefs Xiaoyang Wang, Xiong Zhou, Qiang Li
2015	C	`conf`	A fast and energy efficient binary-to-pseudo CSD converter. ISCAS Yajuan He, Ziji Zhang, Bin Ma, Jinpeng Li, Shaowei Zhen, Ping Luo, Qiang Li
2015	—	`conf`	An 890 mW stacked power amplifier using SiGe HBTs for X-band multifunctional chips. ESSCIRC Chao Liu, Qiang Li, Yihu Li, Xiang Li, Haitao Liu, Yong-Zhong Xiong
2015	J	`jnl`	Central span switching structure for SAR ADC with improved linearity and reduced DAC power. IEICE Electron. Express Junfeng Gao, Guangjun Li, Qiang Li
2015	J	`jnl`	Design Considerations of Ultralow-Voltage Self-Calibrated SAR ADC. IEEE Trans. Circuits Syst. II Express Briefs Xiaoyang Wang, Hai Huang, Qiang Li
2015	J	`jnl`	Energy efficient comparator for successive approximation register ADCs with application to wireless sensor networks. Int. J. Sens. Networks Shitong Yuan, Hai Huang, Qilian Liang, Qiang Li
2014	C	`conf`	A 10-bit 150MS/s SAR ADC with parallel segmented DAC in 65nm CMOS. ISCAS Xiaoyang Wang, Qiang Li
2014	—	`conf`	A 14-bit 100MS/s pipelined A/D converter with 2b interstage redundancy. ISIC Kun Ao, Yajuan He, Liang Li, Yuxin Wang, Qiang Li
2014	—	`conf`	A 250mV 77dB DR 10kHz BW SC ΔΣ Modulator Exploiting Subthreshold OTAs. ESSCIRC Zhiliang Qiao, Xiong Zhou, Qiang Li
2014	—	`conf`	A digital calibration technique for multi-bit-per-stage pipelined ADC. ISIC Yajuan He, Song Wang, Qi Ling, Qiang Li
2014	—	`conf`	A energy-efficient high speed segmented prequantize and bypass DAC for SAR ADCs. MWSCAS Xiaoyang Wang, Xiong Zhou, Qiang Li
2014	—	`conf`	A low-power, CT sigma-delta modulator with a 2b/cycle SAR quantizer. MWSCAS Lishan Lv, Qiang Li
2013	—	`conf`	A 0.25V 97.8fJ/c.-s. 86.5dB SNDR SC ΔΣ modulator in 0.13µm CMOS. MWSCAS Zhiliang Qiao, Xiong Zhou, Qiang Li
2013	C	`conf`	A 0.5V rate-resolution scalable SAR ADC with 63.7dB SFDR. ISCAS Hai Huang, Kun Ao, Zhiyong Guo, Qiang Li
2013	—	`conf`	A 13-bit 200MS/s PIPELINE ADC in 0.13µm CMOS. MWSCAS Junfeng Gao, Bo Chen, Guangjun Li, Qiang Li
2013	C	`conf`	Blind-LMS based digital background calibration for a 14-Bit 200-MS/s pipelined ADC. VLSI-SoC Yajuan He, Bo Chen, Qiang Li
2013	—	`conf`	Hardware-efficient parallel structures for linear-phase FIR digital filter. MWSCAS Jingjing Tian, Guangjun Li, Qiang Li
2013	—	`conf`	High performance SAR ADC with offset and noise tolerance. MWSCAS Junfeng Gao, Guangjun Li, Qiang Li
2012	—	`conf`	A 160mV 670nW 8-bit SAR ADC in 0.13μm CMOS. CICC Xiong Zhou, Qiang Li
2012	—	`conf`	A fast correlation based background digital calibration for pipelined ADCs. APCCAS Chuan-Ping Yan, Guangjun Li, Qiang Li
2012	—	`conf`	A fast-convergence and robust digital calibration algorithm for a 14-bit 200-MS/s hybrid pipelined-SAR ADC. MWSCAS Shan Qing, Guang-Jun Li, Qiang Li
2012	—	`conf`	A multi-rate SerDes transceiver for IEEE 1394b applications. APCCAS Longfei Wei, Jinyue Ji, Haiqi Liu, Qiang Li
2012	J	`jnl`	An Ultrafast Adaptively Biased Capacitorless LDO With Dynamic Charging Control. IEEE Trans. Circuits Syst. II Express Briefs Xin Ming, Qiang Li, Ze-kun Zhou, Bo Zhang
2011	J	`jnl`	Waveform distortion performance evaluation using practical antennas in deterministic multipath impulse radio channels. IET Commun. Zhiyong Guo, Y. P. Zhang, Bo Yan, Qiang Li, Guangjun Li, Habib F. Rashvand
2008	J	`jnl`	Antenna-in-Package and Transmit-Receive Switch for Single-Chip Radio Transceivers of Differential Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. Yue-Ping Zhang, Jun Jun Wang, Qiang Li, Xue Jun Li
2007	J	`jnl`	CMOS T/R Switch Design: Towards Ultra-Wideband and Higher Frequency. IEEE J. Solid State Circuits Qiang Li, Y. P. Zhang
2006	J	`jnl`	A Differential CMOS T/R Switch for Multistandard Applications. IEEE Trans. Circuits Syst. II Express Briefs Yue-Ping Zhang, Qiang Li, Wei Fan, Chew Hoe Ang, He Li