Qian Zhao - RankMe

40 papers A 1B 3C 2Journal 14Unranked 20

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Harmonia: A Unified Framework for Heterogeneous FPGA Acceleration in the Cloud. ASPLOS (2) Luyang Li, Heng Pan, Xinchen Wan, Kai Lv, Zilong Wang, Qian Zhao, Feng Ning, Qingsong Ning, Shideng Zhang, Zhenyu Li, Layong Luo, Gaogang Xie
2023	J	`jnl`	An eFPGA Generation Suite with Customizable Architecture and IDE. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Morihiro Kuga, Qian Zhao, Yuya Nakazato, Motoki Amagasaki, Masahiro Iida
2022	—	`conf`	A Study of Reconfigurable Switch Architecture for Chiplets Interconnection. CANDARW Hui Meng, Qian Zhao, Takaichi Yoshida
2022	J	`jnl`	Reconfigurable Neural Network Accelerator and Simulator for Model Implementation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yasuhiro Nakahara, Masato Kiyama, Motoki Amagasaki, Qian Zhao, Masahiro Iida
2021	—	`conf`	Attention Mechanism Driven YOLOv3 on FPGA Acceleration for Efficient Vision Based Defect Inspection. CSAE Longzhen Yu, Qian Zhao, Zhixian Wang
2021	—	`conf`	Automation of Domain-specific FPGA-IP Generation and Test. HEART Yuya Nakazato, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga
2020	—	`conf`	A Microcode-based Control Unit for Deep Learning Processors. IPDPS Workshops Qian Zhao, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida, Takaichi Yoshida
2020	—	`conf`	Architecture-aware Cost Function for 3D FPGA Placement Using Convolutional Neural Network. CANDAR Qian Zhao, Motoki Amagasaki, Masahiro Iida, Takaichi Yoshida
2019	—	`conf`	A Novel SLM-Based Virtual FPGA Overlay Architecture. MCSoC Theingi Myint, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Masato Kiyama
2019	—	`conf`	A Platform-as-a-Service System for FPGA Education and Development. CompEd Qian Zhao, Takaichi Yoshida
2019	—	`conf`	A Pre-Routing Net Wirelength Prediction Method Using an Optimized Convolutional Neural Network. CANDAR Workshops Ryota Watanabe, Yuki Katsuda, Qian Zhao, Takaichi Yoshida
2019	—	`conf`	A Resource Reduced Application-Specific FPGA Switch. ARC Qian Zhao, Yoshimasa Ohnishi, Masahiro Iida, Takaichi Yoshida
2019	J	`jnl`	A SLM-based overlay architecture for fine-grained virtual FPGA. IEICE Electron. Express Theingi Myint, Motoki Amagasaki, Qian Zhao, Masahiro Iida
2019	—	`conf`	Implementation of FPGA Building Platform as a Cloud Service. HEART Ryota Watanabe, Saika Ura, Qian Zhao, Takaichi Yoshida
2018	—	`conf`	An Adaptable Scheduling for Self-Reconfigurable Objects. CANDAR Workshops Mahdillah Mahdillah, Shinya Nakayama, Qian Zhao, Takaichi Yoshida
2018	J	`jnl`	Enabling FPGA-as-a-Service in the Cloud with hCODE Platform. IEICE Trans. Inf. Syst. Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2018	J	`jnl`	Three Dimensional FPGA Architecture with Fewer TSVs. IEICE Trans. Inf. Syst. Motoki Amagasaki, Masato Ikebe, Qian Zhao, Masahiro Iida, Toshinori Sueyoshi
2017	—	`conf`	A Study of FPGA Virtualization and Accelerator Scheduling. ETCD@ASPLOS Qian Zhao, Masahiro Iida, Toshinori Sueyoshi
2017	J	`jnl`	Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost. IPSJ Trans. Syst. LSI Des. Methodol. Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2017	—	`conf`	hCODE 2.0: An open-source toolkit for building efficient FPGA-enabled clouds. FPT Qian Zhao, Hendarmawan, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2016	J	`jnl`	A Study of Heterogeneous Computing Design Method based on Virtualization Technology. SIGARCH Comput. Archit. News Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2016	—	`conf`	hCODE: An open-source platform for FPGA accelerators. FPT Qian Zhao, Takuya Nakamichi, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2015	J	`jnl`	A 3D FPGA Architecture to Realize Simple Die Stacking. Inf. Media Technol. Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2015	J	`jnl`	A 3D FPGA Architecture to Realize Simple Die Stacking. IPSJ Trans. Syst. LSI Des. Methodol. Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2015	C	`conf`	Architecture exploration of 3D FPGA to minimize internal layer connection. VLSI-SoC Motoki Amagasaki, Yuto Takeuchi, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2015	J	`jnl`	Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC. IEICE Trans. Inf. Syst. Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2015	—	`conf`	Simple wafer stacking 3D-FPGA architecture. ICICDT Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2014	B	`conf`	A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory. FPL Qian Zhao, Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2014	—	`conf`	A novel three-dimensional FPGA architecture with high-speed serial communication links. FPT Takuya Kajiwara, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morituro Kuga, Toshinori Sueyoshi
2013	A	`conf`	A novel FPGA design framework with VLSI post-routing performance analysis (abstract only). FPGA Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2013	—	`conf`	An FPGA design and implementation framework combined with commercial VLSI CADs. ReCoSoC Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2013	B	`conf`	An automatic FPGA design and implementation framework. FPL Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2013	B	`conf`	Defect-robust FPGA architectures for intellectual property cores in system LSI. FPL Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2013	J	`jnl`	FPGA Design Framework Combined with Commercial VLSI CAD. IEICE Trans. Inf. Syst. Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2013	C	`conf`	Three-dimensional stacking FPGA architecture using face-to-face integration. VLSI-SoC Tetsuro Hamada, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2012	J	`jnl`	COGRE: A Novel Compact Logic Cell Architecture for Area Minimization. IEICE Trans. Inf. Syst. Masahiro Iida, Motoki Amagasaki, Yasuhiro Okamoto, Qian Zhao, Toshinori Sueyoshi
2011	J	`jnl`	A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems. IEEE Embed. Syst. Lett. Qian Zhao, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
2011	—	`conf`	A novel reconfigurable logic device base on 3D stack technology. 3DIC Qian Zhao, Yusuke Iwai, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
2010	J	`jnl`	A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core. ACM Trans. Reconfigurable Technol. Syst. Kazuki Inoue, Qian Zhao, Yasuhiro Okamoto, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
2010	—	`conf`	A robust reconfigurable logic device based on less configuration memory logic cell. FPT Qian Zhao, Yoshihiro Ichinomiya, Yasuhiro Okamoto, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi