Qian Chen

11 papers A 2C 4Journal 2Unranked 3
YearRankTypeTitle / Venue / Authors
2023 J jnl
A Single-Channel Voltage-Scalable 8-GS/s 8-b >37.5-dB SNDR Time-Domain ADC With Asynchronous Pipeline Successive Approximation in 28-nm CMOS.
IEEE J. Solid State Circuits
Qian Chen, Chirn Chye Boon, Qing Liu, Yuan Liang
2022 J jnl
A 0.6 V 4 GS/s -56.4 dB THD Voltage-to-Time Converter in 28 nm CMOS.
IEEE Access
Qian Chen, Chirn Chye Boon, Yuan Liang
2021 C conf
Millimetre-Wave and Terahertz Antennas and Directional Coupler Enabled by Wafer-Level Packaging Platform with Interposer.
ISCAS
Yuan Liang, Chirn Chye Boon, Qian Chen, Yangtao Dong
2020 A conf
A 16×128 Stochastic-Binary Processing Element Array for Accelerating Stochastic Dot-Product Computation Using 1-16 Bit-Stream Length.
DATE
Qian Chen, Yuqi Su, Hyunjoon Kim, Taegeun Yoo, Tony Tae-Hyoung Kim, Bongjin Kim
2020 C conf
A 3GS/s Highly Linear Energy Efficient Constant-Slope Based Voltage-to-Time Converter.
ISCAS
Qian Chen, Yuan Liang, Bongjin Kim, Chirn Chye Boon
2020 C conf
A 6bit 1.2GS/s Symmetric Successive Approximation Energy-Efficient Time-to-Digital Converter in 40nm CMOS.
ISCAS
Qian Chen, Yuan Liang, Chirn Chye Boon
2020 C conf
Multi-Channel FSK Inter/Intra-Chip Communication by Exploiting Field-Confined Slow-Wave Transmission Line.
ISCAS
Qian Chen, Chirn Chye Boon, Xueyong Zhang, Chenyang Li, Yuan Liang, Zhe Liu, Ting Guo
2019 — conf
A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation.
ESSCIRC
Hyunjoon Kim, Qian Chen, Taegeun Yoo, Tony Tae-Hyoung Kim, Bongjin Kim
2019 — conf
A 16K SRAM-Based Mixed-Signal In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC.
A-SSCC
Hyunjoon Kim, Qian Chen, Bongjin Kim
2019 — conf
A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks.
ISOCC
Hyunjoon Kim, Qian Chen, Taegeun Yoo, Tony Tae-Hyoung Kim, Bongjin Kim
2019 A conf
A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks.
ISLPED
Taegeun Yoo, Hyunjoon Kim, Qian Chen, Tony Tae-Hyoung Kim, Bongjin Kim