Péter Földesy

21 papers B 1C 6Journal 8Unranked 6
YearRankTypeTitle / Venue / Authors
2026 — conf
Detecting Infant Cries in Noisy NICU Recordings: A Study on SSL Models.
BIOSTEC (1)
Ákos Antal, Péter Földesy, Péter Mihajlik
2020 C conf
Multi-Level Optimization for Enabling Life Critical Visual Inspections of Infants in Resource Limited Environment.
ISCAS
Ákos Zarándy, Péter Földesy, Ádám Nagy, Imre Jánoki, Dániel Terbe, Máté Siket, Miklós Szabó, Judit Varga
2020 J jnl
Non-Contact Vital-Sign Monitoring System for Premature Infants in Neonatal Intensive Care Units.
ERCIM News
Péter Földesy, Imre Jánoki, Ákos Zarándy, Péter Pázmány
2013 J jnl
A hierarchical vision processing architecture oriented to 3D integration of smart camera chips.
J. Syst. Archit.
Ricardo Carmona-Galán, Ákos Zarándy, Csaba Rekeczky, Péter Földesy, Alberto Rodríguez-Pérez, Carlos M. Domínguez-Matas, Jorge Fernández-Berni, Gustavo Liñán Cembrano, Maria Belen Pérez-Verdú, Zoltán Kárász, Manuel Suárez-Cambre, Víctor Manuel Brea Sánchez, Tamás Roska, Ángel Rodríguez-Vázquez
2012 C conf
Characterization of silicon field effect transistor sub-THz detectors for imaging systems.
ISCAS
Péter Földesy
2012 C conf
Test and configuration architecture of a sub-THz CMOS detector array.
DDECS
Péter Földesy, Domonkos Gergelyi, Csaba Fuzy, Gergely Károlyi
2009 — conf
3D multi-layer vision architecture for surveillance and reconnaissance applications.
ECCTD
Péter Földesy, Ricardo Carmona-Galán, Ákos Zarándy, Csaba Rekeczky, Ángel Rodríguez-Vázquez, Tamás Roska
2008 J jnl
Configurable 3D-integrated focal-plane cellular sensor-processor array architecture.
Int. J. Circuit Theory Appl.
Péter Földesy, Ákos Zarándy, Csaba Rekeczky
2007 — conf
3D integrated scalable focal-plane processor array.
ECCTD
Péter Földesy, Ákos Zarándy, Csaba Rekeczky, Tamás Roska
2007 C conf
High performance processor array for image processing.
ISCAS
Péter Földesy, Ákos Zarándy, Csaba Rekeczky, Tamás Roska
2006 J jnl
Digital implementation of cellular sensor-computers.
Int. J. Circuit Theory Appl.
Péter Földesy, Ákos Zarándy, Csaba Rekeczky, Tamás Roska
2005 — conf
Per-pixel integration time controlled image sensor.
ECCTD
Ákos Zarándy, Péter Földesy, Tamás Roska
2005 — conf
Various implementations of topographic, sensory, cellular wave computers.
ISCAS (6)
Ákos Zarándy, Péter Földesy, Péter Szolgay, Szabolcs Tõkés, Csaba Rekeczky, Tamás Roska
2004 B conf
Trends in design of massively parallel coprocessors implemented in digital ASICs.
IJCNN
Péter Földesy
2003 J jnl
PDE-Based Histogram Modification With Embedded Morphological Processing Of The Level-Sets.
J. Circuits Syst. Comput.
György Cserey, Csaba Rekeczky, Péter Földesy
2003 J jnl
The New Framework Of Applications: The Aladdin System.
J. Circuits Syst. Comput.
Ákos Zarándy, Csaba Rekeczky, Péter Földesy, István Szatmári
2002 J jnl
A behavioural modelling technique for visual microprocessor mixed-signal VLSI chips.
Int. J. Circuit Theory Appl.
Péter Földesy, Ángel Rodríguez-Vázquez
2001 — conf
Computing on silicon with trigger waves: experiments on CNN-UM chips.
ISCAS (3)
Csaba Rekeczky, István Szatmári, Péter Földesy
2000 C conf
An analogic CNN engine board with the 64×64 analog I/O CNN-UM chip.
ISCAS
István Szatmári, Ákos Zarándy, Péter Földesy, László Kék
2000 C conf
Implementation of non-linear templates using a decomposition technique by a 0.5 μm CMOS CNN universal chip.
ISCAS
Gustavo Liñán, Péter Földesy, A. Rodrignez-Vazquez, Servando Espejo, Rafael Domínguez-Castro
1997 J jnl
A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage.
IEEE J. Solid State Circuits
Rafael Domínguez-Castro, Servando Espejo, Ángel Rodríguez-Vázquez, Ricardo Carmona, Péter Földesy, Ákos Zarándy, Péter Szolgay, Tamás Szirányi, Tamás Roska