Purushotham Murugappa

11 papers A 2C 6Journal 1Unranked 2
YearRankTypeTitle / Venue / Authors
2019 C conf
A Reconfigurable Architecture for Posit Arithmetic.
DSD
Souradip Sarkar, Purushotham Murugappa, Manil Dev Gomony
2016 J jnl
A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding.
IEEE Trans. Very Large Scale Integr. Syst.
Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Michael Hübner, Jean-Philippe Diguet
2013 — conf
A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context.
ISVLSI
Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet, Jean-Noel Bazin, Michael Hübner
2013 — conf
An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture.
ReCoSoC
Vianney Lapotre, Michael Hübner, Guy Gogniat, Purushotham Murugappa, Amer Baghdadi, Jean-Philippe Diguet
2013 C conf
Optimizations for an efficient reconfiguration of an ASIP-based turbo decoder.
ISCAS
Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet, Jean-Noel Bazin, Michael Hübner
2013 A conf
Parameterized area-efficient multi-standard turbo decoder.
DATE
Purushotham Murugappa, Amer Baghdadi, Michel Jézéquel
2013 C conf
Rapid design and prototyping of a reconfigurable decoder architecture for QC-LDPC codes.
RSP
Purushotham Murugappa, Vianney Lapotre, Amer Baghdadi, Michel Jézéquel
2013 C conf
Stopping-Free Dynamic Configuration of a Multi-ASIP Turbo Decoder.
DSD
Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Michael Hübner, Jean-Philippe Diguet
2012 C conf
FPGA prototyping and performance evaluation of multi-standard Turbo/LDPC Encoding and Decoding.
RSP
Purushotham Murugappa, Jean-Noel Bazin, Amer Baghdadi, Michel Jézéquel
2011 A conf
A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding.
DATE
Purushotham Murugappa, Rachid Al-Khayat, Amer Baghdadi, Michel Jézéquel
2011 C conf
Area and throughput optimized ASIP for multi-standard turbo decoding.
International Symposium on Rapid System Prototyping
Rachid Al-Khayat, Purushotham Murugappa, Amer Baghdadi, Michel Jézéquel