Puneet Gupta

180 papers A* 24A 22B 3C 3Misc 10Journal 78Unranked 40
YearRankTypeTitle / Venue / Authors
2026 J jnl
CATCH: A Cost Analysis Tool for Co-Optimization of Chiplet-Based Heterogeneous Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Alexander Graening, Jonti Talukdar, Saptadeep Pal, Krishnendu Chakrabarty, Puneet Gupta
2026 J jnl
MXFormer: A Microscaling Floating-Point Charge-Trap Transistor Compute-in-Memory Transformer Accelerator.
CoRR
George Karfakis, Samyak Chakrabarty, Vinod Kurian Jacob, Siyun Qiao, Subramanian S. Iyer, Sudhakar Pamarti, Puneet Gupta
2025 J jnl
A 65-nm Digital Stochastic Compute-in-Memory CNN Processor With 8-bit Precision.
IEEE J. Solid State Circuits
Jiyue Yang, Tianmu Li, Wojciech Romaszkan, Puneet Gupta, Sudhakar Pamarti
2025 J jnl
A Comparative Analysis of Low Temperature and Room Temperature Circuit Operation.
IEEE Trans. Very Large Scale Integr. Syst.
Zhichao Chen, Ali H. Hassan, Rhesa Muhammad Ramadhan, Yingheng Li, Chih-Kong Ken Yang, Sudhakar Pamarti, Puneet Gupta
2025 J jnl
CATCH: a Cost Analysis Tool for Co-optimization of chiplet-based Heterogeneous systems.
CoRR
Alexander Graening, Jonti Talukdar, Saptadeep Pal, Krishnendu Chakrabarty, Puneet Gupta
2025 J jnl
CIMPool: Scalable Neural Network Acceleration for Compute-In-Memory using Weight Pools.
CoRR
Shurui Li, Puneet Gupta
2025 J jnl
ChipletPart: Scalable Cost-Aware Partitioning for 2.5D Systems.
CoRR
Alexander Graening, Puneet Gupta, Andrew B. Kahng, Bodhisatta Pramanik, Zhiang Wang
2025 A* conf
FRED: A Wafer-scale Fabric for 3D Parallel DNN Training.
ISCA
Saeed Rashidi, William Won, Sudarshan Srinivasan, Puneet Gupta, Tushar Krishna
2025 J jnl
Learned Approximate Computing: Algorithm Hardware Co-Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Egor Glukhov, Tianmu Li, Vaibhav Gupta, Puneet Gupta
2025 J jnl
Optimizing Thermal Performance in 2.5D Systems Using Embedded Isolators.
IEEE J. Emerg. Sel. Topics Circuits Syst.
George Karfakis, Myriam Bouzidi, Yunhyeok Im, Alexander Graening, Suresh K. Sitaraman, Puneet Gupta
2025 J jnl
RAPID-LLM: Resilience-Aware Performance analysis of Infrastructure for Distributed LLM Training and Inference.
CoRR
George Karfakis, Faraz Tahmasebi, Binglu Chen, Lime Yao, Saptarshi Mitra, Tianyue Pan, Hyoukjun Kwon, Puneet Gupta
2025 J jnl
YAP+: Pad-Layout-Aware Yield Modeling and Simulation for Hybrid Bonding.
CoRR
Zhichao Chen, Puneet Gupta
2024 — conf
A 278-514M Event/s ADC-Less Stochastic Compute-In-Memory Convolution Accelerator for Event Camera.
VLSI Technology and Circuits
Jiyue Yang, Alexander Graening, Wojciech Romaszkan, Vinod Kurian Jacob, Puneet Gupta, Sudhakar Pamarti
2024 J jnl
Achieving DRAM-Like PCM by Trading Off Capacity for Latency.
IEEE Trans. Computers
Irina Alam, Puneet Gupta
2024 — conf
Cryogenic Alternative: CMOS Versus Dynamic-Based Logic.
MWSCAS
Ali H. Hassan, Puneet Gupta, Sudhakar Pamarti, Chih-Kong Ken Yang
2024 J jnl
DeepFlow: A Cross-Stack Pathfinding Framework for Distributed AI Systems.
ACM Trans. Design Autom. Electr. Syst.
Newsha Ardalani, Saptadeep Pal, Puneet Gupta
2024 J jnl
FRED: Flexible REduction-Distribution Interconnect and Communication Implementation for Wafer-Scale Distributed Training of DNN Models.
CoRR
Saeed Rashidi, William Won, Sudarshan Srinivasan, Puneet Gupta, Tushar Krishna
2024 — conf
Novel Energy-Efficient and Latency-Improved PVT Tolerant Read Scheme for SRAM Design in Video Processing and Machine Learning Applications.
MWSCAS
Soumitra Pal, Jiyue Yang, Stephen Bauer, Puneet Gupta, Sudhakar Pamarti
2024 J jnl
SCIMITAR: Stochastic Computing In-Memory In-Situ Tracking ARchitecture for Event-Based Cameras.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wojciech Romaszkan, Jiyue Yang, Alexander Graening, Vinod Kurian Jacob, Jishnu Sen, Sudhakar Pamarti, Puneet Gupta
2023 A* conf
Chiplets: How Small is too Small?
DAC
Alexander Graening, Saptadeep Pal, Puneet Gupta
2023 J jnl
Cost-Driven Hardware-Software Co-Optimization of Machine Learning Pipelines.
CoRR
Ravit Sharma, Wojciech Romaszkan, Feiqian Zhu, Puneet Gupta, Ankur Mehta
2023 J jnl
DRDebug: Automated Design Rule Debugging.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irina Alam, Tianmu Li, Sean Brock, Puneet Gupta
2023 A* conf
PhotoFourier: A Photonic Joint Transform Correlator-Based Neural Network Accelerator.
HPCA
Shurui Li, Hangbo Yang, Chee Wei Wong, Volker J. Sorger, Puneet Gupta
2023 J jnl
REX-SC: Range-Extended Stochastic Computing Accumulation for Neural Network Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tianmu Li, Wojciech Romaszkan, Sudhakar Pamarti, Puneet Gupta
2023 A* conf
ReFOCUS: Reusing Light for Efficient Fourier Optics-Based Photonic Neural Network Accelerator.
MICRO
Shurui Li, Hangbo Yang, Chee Wei Wong, Volker J. Sorger, Puneet Gupta
2023 J jnl
Training Neural Networks for Execution on Approximate Hardware.
CoRR
Tianmu Li, Shurui Li, Puneet Gupta
2022 — conf
Bit-serial Weight Pools: Compression and Arbitrary Precision Execution of Neural Networks on Resource Constrained Processors.
MLSys
Shurui Li, Puneet Gupta
2022 J jnl
Bit-serial Weight Pools: Compression and Arbitrary Precision Execution of Neural Networks on Resource Constrained Processors.
CoRR
Shurui Li, Puneet Gupta
2022 A conf
COMET: On-die and In-controller Collaborative Memory ECC Technique for Safer and Stronger Correction of DRAM Errors.
DSN
Irina Alam, Puneet Gupta
2022 J jnl
DeepFlow: A Cross-Stack Pathfinding Framework for Distributed AI Systems.
CoRR
Newsha Ardalani, Saptadeep Pal, Puneet Gupta
2022 A conf
LAC: Learned Approximate Computing.
DATE
Vaibhav Gupta, Tianmu Li, Puneet Gupta
2022 J jnl
PhotoFourier: A Photonic Joint Transform Correlator-Based Neural Network Accelerator.
CoRR
Shurui Li, Hangbo Yang, Chee Wei Wong, Volker J. Sorger, Puneet Gupta
2022 J jnl
SASCHA - Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wojciech Romaszkan, Tianmu Li, Puneet Gupta
2021 — conf
A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM.
ESSCIRC
Jiyue Yang, Di Wu, Albert Lee, Seyed Armin Razavi, Puneet Gupta, Kang L. Wang, Sudhakar Pamarti
2021 — conf
A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM.
ESSDERC
Jiyue Yang, Di Wu, Albert Lee, Seyed Armin Razavi, Puneet Gupta, Kang L. Wang, Sudhakar Pamarti
2021 J jnl
Adaptive MRAM Write and Read with MTJ Variation Monitor.
IEEE Trans. Emerg. Top. Comput.
Shaodi Wang, Hochul Lee, Cecile Grezes, Pedram Khalili Amiri, Kang L. Wang, Puneet Gupta
2021 J jnl
Batch Processing and Data Streaming Fourier-based Convolutional Neural Network Accelerator.
CoRR
Zibo Hu, Shurui Li, Russell L. T. Schwartz, Maria Solyanik-Gorgone, Mario Miscuglio, Puneet Gupta, Volker J. Sorger
2021 A* conf
Designing a 2048-Chiplet, 14336-Core Waferscale Processor.
DAC
Saptadeep Pal, Jingyang Liu, Irina Alam, Nicholas Cebry, Haris Suhail, Shi Bu, Subramanian S. Iyer, Sudhakar Pamarti, Rakesh Kumar, Puneet Gupta
2021 A conf
GEO: Generation and Execution Optimized Stochastic Computing Accelerator for Neural Networks.
DATE
Tianmu Li, Wojciech Romaszkan, Sudhakar Pamarti, Puneet Gupta
2021 J jnl
SWIS - Shared Weight bIt Sparsity for Efficient Neural Network Acceleration.
CoRR
Shurui Li, Wojciech Romaszkan, Alexander Graening, Puneet Gupta
2020 J jnl
3PXNet: Pruned-Permuted-Packed XNOR Networks for Edge Machine Learning.
ACM Trans. Embed. Comput. Syst.
Wojciech Romaszkan, Tianmu Li, Puneet Gupta
2020 A conf
ACOUSTIC: Accelerating Convolutional Neural Networks through Or-Unipolar Skipped Stochastic Computing.
DATE
Wojciech Romaszkan, Tianmu Li, Tristan Melton, Sudhakar Pamarti, Puneet Gupta
2020 J jnl
Channel Tiling for Improved Performance and Accuracy of Optical Neural Network Accelerators.
CoRR
Shurui Li, Mario Miscuglio, Volker J. Sorger, Puneet Gupta
2020 J jnl
Design Space Exploration for Chiplet-Assembly-Based Processors.
IEEE Trans. Very Large Scale Integr. Syst.
Saptadeep Pal, Daniel Petrisko, Rakesh Kumar, Puneet Gupta
2020 — conf
Pathfinding for 2.5D interconnect technologies.
SLIP
Saptadeep Pal, Puneet Gupta
2020 J jnl
Reverse Engineering for 2.5-D Split Manufactured ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wei-Che Wang, Yizhang Wu, Puneet Gupta
2020 — conf
SAME-Infer: Software Assisted Memory Resilience for Efficient Inference at the Edge.
MEMSYS
Irina Alam, Puneet Gupta
2020 J jnl
SLATE: A Secure Lightweight Entity Authentication Hardware Primitive.
IEEE Trans. Inf. Forensics Secur.
Wei-Che Wang, Yair Yona, Yizhang Wu, Suhas N. Diggavi, Puneet Gupta
2019 A* conf
Architecting Waferscale Processors - A GPU Case Study.
HPCA
Saptadeep Pal, Daniel Petrisko, Matthew Tomei, Puneet Gupta, Subramanian S. Iyer, Rakesh Kumar
2019 — conf
Compression with multi-ECC: enhanced error resiliency for magnetic memories.
MEMSYS
Irina Alam, Saptadeep Pal, Puneet Gupta
2019 J jnl
Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories.
IEEE Trans. Inf. Theory
Clayton Schoeny, Frederic Sala, Mark Gottscho, Irina Alam, Puneet Gupta, Lara Dolecek
2019 J jnl
Optimizing Multi-GPU Parallelization Strategies for Deep Learning Training.
CoRR
Saptadeep Pal, Eiman Ebrahimi, Arslan Zulfiqar, Yaosheng Fu, Victor Zhang, Szymon Migacz, David W. Nellans, Puneet Gupta
2019 J jnl
Optimizing Multi-GPU Parallelization Strategies for Deep Learning Training.
IEEE Micro
Saptadeep Pal, Eiman Ebrahimi, Arslan Zulfiqar, Yaosheng Fu, Victor Zhang, Szymon Migacz, David W. Nellans, Puneet Gupta
2019 J jnl
Variability Expeditions: A Retrospective.
IEEE Des. Test
Rajesh K. Gupta, Subhasish Mitra, Puneet Gupta
2018 A* conf
A Case for Packageless Processors.
HPCA
Saptadeep Pal, Daniel Petrisko, Adeel Ahmad Bajwa, Puneet Gupta, Subramanian S. Iyer, Rakesh Kumar
2018 J jnl
Assessing Layout Density Benefits of Vertical Channel Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wei-Che Wang, Charles Zhao, Puneet Gupta
2018 J jnl
Design and Analysis of Stability-Guaranteed PUFs.
IEEE Trans. Inf. Forensics Secur.
Wei-Che Wang, Yair Yona, Suhas N. Diggavi, Puneet Gupta
2018 B conf
Error Correction and Detection for Computing Memories Using System Side Information.
ITW
Clayton Schoeny, Irina Alam, Mark Gottscho, Puneet Gupta, Lara Dolecek
2018 J jnl
Implementation and Analysis of Stable PUFs Using Gate Oxide Breakdown.
CoRR
Wei-Che Wang, Yair Yona, Yizhang Wu, Suhas N. Diggavi, Puneet Gupta
2018 — conf
Parity++: Lightweight Error Correction for Last Level Caches.
DSN Workshops
Irina Alam, Clayton Schoeny, Lara Dolecek, Puneet Gupta
2017 J jnl
A Word Line Pulse Circuit Technique for Reliable Magnetoelectric Random Access Memory.
IEEE Trans. Very Large Scale Integr. Syst.
Hochul Lee, Albert Lee, Shaodi Wang, Farbod Ebrahimi, Puneet Gupta, Pedram Khalili Amiri, Kang L. Wang
2017 — conf
Advanced Packaging and Heterogeneous Integration to Reboot Computing.
ICRC
Saptadeep Pal, Subramanian S. Iyer, Puneet Gupta
2017 J jnl
Assessing Benefits of a Buried Interconnect Layer in Digital Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Liheng Zhu, Yasmine Badr, Shaodi Wang, Subramanian S. Iyer, Puneet Gupta
2017 J jnl
Benchmarking of Mask Fracturing Heuristics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tuck-Boon Chan, Puneet Gupta, Kwangsoo Han, Abde Ali Kagalwalla, Andrew B. Kahng
2017 B conf
Context-aware resiliency: Unequal message protection for random-access memories.
ITW
Clayton Schoeny, Frederic Sala, Mark Gottscho, Irina Alam, Puneet Gupta, Lara Dolecek
2017 J jnl
Design and Analysis of Stability-Guaranteed PUFs.
CoRR
Wei-Che Wang, Yair Yona, Suhas N. Diggavi, Puneet Gupta
2017 A conf
Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing.
DATE
Shaodi Wang, Saptadeep Pal, Tianmu Li, Andrew Pan, Cecile Grezes, Pedram Khalili Amiri, Kang L. Wang, Puneet Gupta
2017 — conf
Implementation of stable PUFs using gate oxide breakdown.
AsianHOST
Wei-Che Wang, Yair Yona, Yizhang Wu, Szu-Yao Hung, Suhas N. Diggavi, Puneet Gupta
2017 J jnl
Low-Cost Memory Fault Tolerance for IoT Devices.
ACM Trans. Embed. Comput. Syst.
Mark Gottscho, Irina Alam, Clayton Schoeny, Lara Dolecek, Puneet Gupta
2017 J jnl
Mask Assignment and DSA Grouping for DSA-MP Hybrid Lithography for Sub-7 nm Contact/Via Holes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yasmine Badr, Andres Torres, Puneet Gupta
2017 J jnl
Measuring the Impact of Memory Errors on Application Performance.
IEEE Comput. Archit. Lett.
Mark Gottscho, Mohammed Shoaib, Sriram Govindan, Bikash Sharma, Di Wang, Puneet Gupta
2017 J jnl
System-Level Dynamic Variation Margining in Presence of Monitoring and Actuation.
IEEE Embed. Syst. Lett.
Liangzhen Lai, Puneet Gupta
2016 J jnl
An Evaluation Framework for Nanotransfer Printing-Based Feature-Level Heterogeneous Integration in VLSI Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Greg Leung, Shaodi Wang, Andrew Pan, Puneet Gupta, Chi On Chui
2016 J jnl
Comparative Evaluation of Spin-Transfer-Torque and Magnetoelectric Random Access Memory.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Shaodi Wang, Hochul Lee, Farbod Ebrahimi, P. Khalili Amiri, Kang L. Wang, Puneet Gupta
2016 J jnl
Efficient Layout Generation and Design Evaluation of Vertical Channel Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wei-Che Wang, Puneet Gupta
2016 — conf
Hardware Reliability margining for the dark silicon era.
ASP-DAC
Liangzhen Lai, Puneet Gupta
2016 — conf
LEDPUF: Stability-guaranteed physical unclonable functions through locally enhanced defectivity.
HOST
Wei-Che Wang, Yair Yona, Suhas N. Diggavi, Puneet Gupta
2016 J jnl
MEMRES: A Fast Memory System Reliability Simulator.
IEEE Trans. Reliab.
Shaodi Wang, Henry Chaohong Hu, Hongzhong Zheng, Puneet Gupta
2016 A* conf
MTJ variation monitor-assisted adaptive MRAM write.
DAC
Shaodi Wang, Hochul Lee, Cecile Grezes, Pedram Khalili, Kang L. Wang, Puneet Gupta
2016 A conf
Multi-story power distribution networks for GPUs.
DATE
Qixiang Zhang, Liangzhen Lai, Mark Gottscho, Puneet Gupta
2016 J jnl
PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices.
IEEE Trans. Very Large Scale Integr. Syst.
Shaodi Wang, Andrew Pan, Chi On Chui, Puneet Gupta
2016 — conf
Software-Defined Error-Correcting Codes.
DSN Workshops
Mark Gottscho, Clayton Schoeny, Lara Dolecek, Puneet Gupta
2016 B conf
X-Mem: A cross-platform and extensible memory characterization tool for the cloud.
ISPASS
Mark Gottscho, Sriram Govindan, Bikash Sharma, Mohammed Shoaib, Puneet Gupta
2015 A conf
Cyberphysical-system-on-chip (CPSoC): a self-aware MPSoC paradigm with cross-layer virtual sensing and actuation.
DATE
Santanu Sarma, Nikil D. Dutt, Puneet Gupta, Nalini Venkatasubramanian, Alexandru Nicolau
2015 J jnl
DPCS: Dynamic Power/Capacity Scaling for SRAM Caches in the Nanoscale Era.
ACM Trans. Archit. Code Optim.
Mark Gottscho, Abbas BanaiyanMofrad, Nikil D. Dutt, Alex Nicolau, Puneet Gupta
2015 A* conf
Effective model-based mask fracturing for mask cost reduction.
DAC
Abde Ali Kagalwalla, Puneet Gupta
2015 Misc conf
Evaluating and exploiting impacts of dynamic power management schemes on system reliability.
CASES
Liangzhen Lai, Vikas Chandra, Puneet Gupta
2015 A* conf
Mask assignment and synthesis of DSA-MP hybrid lithography for sub-7nm contacts/vias.
DAC
Yasmine Badr, Andres Torres, Puneet Gupta
2015 J jnl
NSF expedition on variability-aware software: Recent results and contributions.
it Inf. Technol.
Lucas Francisco Wanner, Liangzhen Lai, Abbas Rahimi, Mark Gottscho, Pietro Mercati, Chu-Hsiang Huang, Frederic Sala, Yuvraj Agarwal, Lara Dolecek, Nikil D. Dutt, Puneet Gupta, Rajesh K. Gupta, Ranjit Jhala, Rakesh Kumar, Sorin Lerner, Subhasish Mitra, Alexandru Nicolau, Tajana Simunic Rosing, Mani B. Srivastava, Steven Swanson, Dennis Sylvester, Yuanyuan Zhou
2015 J jnl
ViPZonE: Hardware Power Variability-Aware Virtual Memory Management for Energy Savings.
IEEE Trans. Computers
Mark Gottscho, Luis Angel D. Bathen, Nikil D. Dutt, Alex Nicolau, Puneet Gupta
2014 — conf
A Case for Battery Charging-Aware Power Management and Deferrable Task Scheduling in Smartphones.
HotPower
Salma Elmalaki, Mark Gottscho, Puneet Gupta, Mani B. Srivastava
2014 — conf
Accurate and inexpensive performance monitoring for variability-aware systems.
ASP-DAC
Liangzhen Lai, Puneet Gupta
2014 J jnl
BTI-Gater: An Aging-Resilient Clock Gating Methodology.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Liangzhen Lai, Vikas Chandra, Robert C. Aitken, Puneet Gupta
2014 A conf
Benchmarking of mask fracturing heuristics.
ICCAD
Tuck-Boon Chan, Puneet Gupta, Kwangsoo Han, Abde Ali Kagalwalla, Andrew B. Kahng, Emile Sahouria
2014 — conf
Comprehensive die-level assessment of design rules and layouts.
ASP-DAC
Rani S. Ghaida, Yasmine Badr, Mukul Gupta, Ning Jin, Puneet Gupta
2014 — conf
EUV-CDA: Pattern shift aware critical density analysis for EUV mask layouts.
ASP-DAC
Abde Ali Kagalwalla, Michale Lam, Kostas Adam, Puneet Gupta
2014 A conf
Efficient layout generation and evaluation of vertical channel devices.
ICCAD
Wei-Che Wang, Puneet Gupta
2014 — conf
Minimizing clock domain crossing in Network on Chip interconnect.
ISQED
Parag Kulkarni, Puneet Gupta, Rudy Beraha
2014 A* conf
Multi-Layer Memory Resiliency.
DAC
Nikil D. Dutt, Puneet Gupta, Alex Nicolau, Abbas BanaiyanMofrad, Mark Gottscho, Majid Shoushtari
2014 Misc conf
On-chip self-awareness using Cyberphysical-Systems-on-Chip (CPSoC).
CODES+ISSS
Santanu Sarma, Nikil D. Dutt, Puneet Gupta, Alexandru Nicolau, Nalini Venkatasubramanian
2014 — conf
PROCEED: A pareto optimization-based circuit-level evaluator for emerging devices.
ASP-DAC
Shaodi Wang, Andrew Pan, Chi On Chui, Puneet Gupta
2014 C conf
Pattern-restricted design at 10nm and beyond.
ICCD
Rani S. Ghaida, Yasmine Badr, Puneet Gupta
2014 A* conf
Power / Capacity Scaling: Energy Savings With Simple Fault-Tolerant Caches.
DAC
Mark Gottscho, Abbas BanaiyanMofrad, Nikil D. Dutt, Alex Nicolau, Puneet Gupta
2014 J jnl
SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Liangzhen Lai, Vikas Chandra, Robert C. Aitken, Puneet Gupta
2014 J jnl
Statistical timing and power analysis of VLSI considering non-linear dependence.
Integr.
Lerong Cheng, Wenyao Xu, Fengbo Ren, Fang Gong, Puneet Gupta, Lei He
2014 J jnl
Synthesis and Analysis of Design-Dependent Ring Oscillator (DDRO) Performance Monitors.
IEEE Trans. Very Large Scale Integr. Syst.
Tuck-Boon Chan, Puneet Gupta, Andrew B. Kahng, Liangzhen Lai
2013 Misc conf
ARGO: Aging-aware GPGPU register file allocation.
CODES+ISSS
Majid Namaki-Shoushtari, Abbas Rahimi, Nikil D. Dutt, Puneet Gupta, Rajesh K. Gupta
2013 — conf
Design for nanoscale patterning.
CICC
Puneet Gupta
2013 J jnl
Hardware Variability-Aware Duty Cycling for Embedded Sensors.
IEEE Trans. Very Large Scale Integr. Syst.
Lucas Francisco Wanner, Charwak Apte, Rahul Balani, Puneet Gupta, Mani B. Srivastava
2013 J jnl
Layout Decomposition and Legalization for Double-Patterning Technology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars Liebmann, Puneet Gupta
2013 A* conf
Reliable on-chip systems in the nano-era: lessons learnt and future trends.
DAC
Jörg Henkel, Lars Bauer, Nikil D. Dutt, Puneet Gupta, Sani R. Nassif, Muhammad Shafique, Mehdi Baradaran Tahoori, Norbert Wehn
2013 A conf
Role of design in multiple patterning: technology development, design enablement and process control.
DATE
Rani S. Ghaida, Puneet Gupta
2013 A conf
SlackProbe: a low overhead in situ on-line timing slack monitoring methodology.
DATE
Liangzhen Lai, Vikas Chandra, Robert C. Aitken, Puneet Gupta
2013 C conf
Towards analyzing and improving robustness of software applications to intermittent and permanent faults in hardware.
ICCD
Ankur Sharma, Joseph Sloan, Lucas Francisco Wanner, Salma Elmalaki, Mani B. Srivastava, Puneet Gupta
2013 J jnl
Underdesigned and Opportunistic Computing in Presence of Hardware Variability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Puneet Gupta, Yuvraj Agarwal, Lara Dolecek, Nikil D. Dutt, Rajesh K. Gupta, Rakesh Kumar, Subhasish Mitra, Alexandru Nicolau, Tajana Simunic Rosing, Mani B. Srivastava, Steven Swanson, Dennis Sylvester
2013 Misc conf
VarEMU: An emulation testbed for variability-aware software.
CODES+ISSS
Lucas Francisco Wanner, Salma Elmalaki, Liangzhen Lai, Puneet Gupta, Mani B. Srivastava
2013 — conf
Variability-aware memory management for nanoscale computing.
ASP-DAC
Nikil D. Dutt, Puneet Gupta, Alex Nicolau, Luis Angel D. Bathen, Mark Gottscho
2012 A conf
A methodology for the early exploration of design rules for multiple-patterning technologies.
ICCAD
Rani S. Ghaida, Tanaya Sahu, Parag Kulkarni, Puneet Gupta
2012 J jnl
AppAdapt: Opportunistic Application Adaptation in Presence of Hardware Variation.
IEEE Trans. Very Large Scale Integr. Syst.
Aashish Pant, Puneet Gupta, Mihaela van der Schaar
2012 — conf
DDRO: A novel performance monitoring methodology based on design-dependent ring oscillators.
ISQED
Tuck-Boon Chan, Puneet Gupta, Andrew B. Kahng, Liangzhen Lai
2012 J jnl
DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rani S. Ghaida, Puneet Gupta
2012 J jnl
Design-Aware Mask Inspection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Abde Ali Kagalwalla, Puneet Gupta, Christopher J. Progler, Steve McDonald
2012 J jnl
Discrete Circuit Optimization: Library Based Gate Sizing and Threshold Voltage Assignment.
Found. Trends Electron. Des. Autom.
John Lee, Puneet Gupta
2012 J jnl
Discrete sizing for leakage power optimization in physical design: A comparative study.
ACM Trans. Design Autom. Electr. Syst.
Santiago Mok, John Lee, Puneet Gupta
2012 J jnl
ECO cost measurement and incremental gate sizing for late process changes.
ACM Trans. Design Autom. Electr. Syst.
John Lee, Puneet Gupta
2012 A conf
Impact of range and precision in technology on cell-based design.
ICCAD
John Lee, Puneet Gupta
2012 — conf
O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction.
ICICDT
Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars W. Liebmann, Puneet Gupta
2012 — conf
Parametric Hierarchy Recovery in Layout Extracted Netlists.
ISVLSI
John Lee, Puneet Gupta, Fedor Pikus
2012 J jnl
Power Variability in Contemporary DRAMs.
IEEE Embed. Syst. Lett.
Mark Gottscho, Abde Ali Kagalwalla, Puneet Gupta
2012 A conf
VaMV: Variability-aware Memory Virtualization.
DATE
Luis Angel D. Bathen, Nikil D. Dutt, Alex Nicolau, Puneet Gupta
2012 Misc conf
ViPZonE: OS-level memory variability-driven physical address zoning for energy savings.
CODES+ISSS
Luis Angel D. Bathen, Mark Gottscho, Nikil D. Dutt, Alex Nicolau, Puneet Gupta
2011 A conf
A framework for double patterning-enabled design.
ICCAD
Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars Liebmann, Puneet Gupta
2011 A conf
On the efficacy of NBTI mitigation techniques.
DATE
Tuck-Boon Chan, John Sartori, Puneet Gupta, Rakesh Kumar
2011 J jnl
Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lerong Cheng, Puneet Gupta, Costas J. Spanos, Kun Qian, Lei He
2011 J jnl
Trading Accuracy for Power in a Multiplier Architecture.
J. Low Power Electron.
Parag Kulkarni, Puneet Gupta, Milos D. Ercegovac
2011 Misc conf
Trading Accuracy for Power with an Underdesigned Multiplier Architecture.
VLSI Design
Parag Kulkarni, Puneet Gupta, Milos D. Ercegovac
2011 — conf
Underdesigned and Opportunistic Computing.
Asian Test Symposium
Puneet Gupta, Rajesh K. Gupta
2011 A conf
Variability-aware duty cycle scheduling in long running embedded sensing systems.
DATE
Lucas Francisco Wanner, Rahul Balani, Sadaf Zahedi, Charwak Apte, Puneet Gupta, Mani B. Srivastava
2010 A conf
Design dependent process monitoring for back-end manufacturing cost reduction.
ICCAD
Tuck-Boon Chan, Aashish Pant, Lerong Cheng, Puneet Gupta
2010 A conf
Design-aware mask inspection.
ICCAD
Abde Ali Kagalwalla, Puneet Gupta, Christopher J. Progler, Steve McDonald
2010 Misc conf
Electrical Modeling of Lithographic Imperfections.
VLSI Design
Tuck-Boon Chan, Rani S. Ghaida, Puneet Gupta
2010 J jnl
Evaluating Statistical Power Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jason Cong, Puneet Gupta, John Lee
2010 A* conf
Eyecharts: constructive benchmarking of gate sizing heuristics.
DAC
Puneet Gupta, Andrew B. Kahng, Amarnath Kasibhatla, Puneet Sharma
2010 C conf
Incremental gate sizing for late process changes.
ICCD
John Lee, Puneet Gupta
2010 Misc conf
On Electrical Modeling of Imperfect Diffusion Patterning.
VLSI Design
Tuck-Boon Chan, Puneet Gupta
2010 — conf
On confidence in characterization and application of variation models.
ASP-DAC
Lerong Cheng, Puneet Gupta, Lei He
2010 — conf
Software adaptation in quality sensitive applications to deal with hardware variability.
ACM Great Lakes Symposium on VLSI
Aashish Pant, Puneet Gupta, Mihaela van der Schaar
2010 — conf
Variation-aware speed binning of multi-core processors.
ISQED
John Sartori, Aashish Pant, Rakesh Kumar, Puneet Gupta
2009 A conf
A framework for early and systematic evaluation of design rules.
ICCAD
Rani S. Ghaida, Puneet Gupta
2009 — conf
Accounting for non-linear dependence using function driven component analysis.
ASP-DAC
Lerong Cheng, Puneet Gupta, Lei He
2009 J jnl
Efficient Additive Statistical Leakage Estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lerong Cheng, Puneet Gupta, Lei He
2009 — conf
On the futility of statistical power optimization.
ASP-DAC
Jason Cong, Puneet Gupta, John Lee
2009 A* conf
Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability.
DAC
Lerong Cheng, Puneet Gupta, Costas J. Spanos, Kun Qian, Lei He
2008 A* conf
Bounded-lifetime integrated circuits.
DAC
Puneet Gupta, Andrew B. Kahng
2008 — conf
Investigation of diffusion rounding for post-lithography analysis.
ASP-DAC
Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester
2007 J jnl
Detailed Placement for Enhanced Control of Resist and Etch CDs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Puneet Gupta, Andrew B. Kahng, Chul-Hong Park
2007 A* conf
Line-End Shortening is Not Always a Failure.
DAC
Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester
2007 J jnl
Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester
2006 Misc conf
Efficient Design and Analysis of Robust Power Distribution Meshes.
VLSI Design
Puneet Gupta, Andrew B. Kahng
2006 J jnl
Gate-length biasing for runtime-leakage control.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester
2006 A* conf
Standard cell library optimization for leakage reduction.
DAC
Saumil Shah, Puneet Gupta, Andrew B. Kahng
2006 J jnl
Wafer Topography-Aware Optical Proximity Correction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Puneet Gupta, Andrew B. Kahng, Chul-Hong Park, Kambiz Samadi, Xu Xu
2005 — conf
A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology.
ISQED
Puneet Gupta, Andrew B. Kahng, Puneet Sharma
2005 A* conf
Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions.
DAC
Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester
2005 — conf
Detailed placement for improved depth of focus and CD control.
ASP-DAC
Puneet Gupta, Andrew B. Kahng, Chul-Hong Park
2005 J jnl
Layout-aware scan chain synthesis for improved path delay fault coverage.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma
2005 — conf
Performance Driven OPC for Mask Cost Reduction.
ISQED
Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang
2005 J jnl
Routing-aware scan chain ordering.
ACM Trans. Design Autom. Electr. Syst.
Puneet Gupta, Andrew B. Kahng, Stefanus Mantik
2004 — conf
Investigation of performance metrics for interconnect stack architectures.
SLIP
Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester
2004 A* conf
Selective gate-length biasing for cost-effective runtime leakage control.
DAC
Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester
2004 A* conf
Toward a methodology for manufacturability-driven design rule exploration.
DAC
Luigi Capodieci, Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang
2004 A* conf
Toward a systematic-variation aware timing methodology.
DAC
Puneet Gupta, Fook-Luen Heng
2004 Misc conf
Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling.
VLSI Design
Puneet Gupta, Andrew B. Kahng
2003 — conf
A Proposal for Routing-Based Timing-Driven Scan Chain Ordering.
ISQED
Puneet Gupta, Andrew B. Kahng, Stefanus Mantik
2003 A* conf
A cost-driven lithographic correction methodology based on off-the-shelf sizing tools.
DAC
Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang
2003 A conf
Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage.
ICCAD
Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma
2003 A conf
Manufacturing-Aware Physical Design.
ICCAD
Puneet Gupta, Andrew B. Kahng
2003 A* conf
Performance-impact limited area fill synthesis.
DAC
Yu Chen, Puneet Gupta, Andrew B. Kahng
2003 — conf
Quantifying Error in Dynamic Power Estimation of CMOS Circuits.
ISQED
Puneet Gupta, Andrew B. Kahng
2003 — conf
Routing-aware scan chain ordering.
ASP-DAC
Puneet Gupta, Andrew B. Kahng, Stefanus Mantik