| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2026 | J | jnl |
Integr.
|
| 2020 | J | jnl |
J. Parallel Distributed Comput.
|
| 2019 | J | jnl |
Real Time Syst.
|
| 2018 | J | jnl |
Integr.
|
| 2018 | J | jnl |
J. Parallel Distributed Comput.
|
| 2018 | J | jnl |
Integr.
|
| 2018 | J | jnl |
IEEE Trans. Computers
|
| 2017 | J | jnl |
J. Syst. Archit.
|
| 2017 | J | jnl |
Low Power Low Latency Floorplan‐aware Path Synthesis in Application-Specific Network-on-Chip Design.
Integr.
|
| 2016 | — | conf |
VDAT
|
| 2016 | — | conf |
RAIT
|
| 2013 | — | conf |
ISED
|
| 2012 | — | conf |
VDAT
|
| 2012 | — | conf |
SoCC
|