Priyadarsan Patra

30 papers A* 1A 2C 2Misc 3Journal 9Unranked 13

Year	Rank	Type	Title / Venue / Authors
2026	Misc	`conf`	Fast and Accurate Flow Priority Detection in Encrypted Networks using Reinforcement Learning. COMSNETS S. Varun, Sadanand Vishwas, Uday Trivedi, Raviraj Bhat, Kuldeepsinh Dilipsinh Rana, Priyadarsan Patra
2023	—	`conf`	Office of the Pro Vice Chancellor. ISED Priyadarsan Patra
2020	J	`jnl`	Enabling Hardware Performance Counters for Microkernel-Based Virtualization on Embedded Systems. IEEE Access Deepa Mathew, Bijoy Antony Jose, Jimson Mathew, Priyadarsan Patra
2020	J	`jnl`	In silico ranking of phenolics for therapeutic effectiveness on cancer stem cells. BMC Bioinform. Monalisa Mandal, Sanjeeb Kumar Sahoo, Priyadarsan Patra, Saurav Mallik, Zhongming Zhao
2019	J	`jnl`	Performance Analysis of Microkernel Based Virtualization Techniques on Embedded Systems. J. Low Power Electron. Deepa Mathew, Bijoy Antony Jose, Priyadarsan Patra
2019	J	`jnl`	Selected Articles from the ISED 2018 Conference. J. Low Power Electron. Jimson Mathew, Bijoy Antony Jose, Priyadarsan Patra
2019	—	`conf`	Techniques for Debug of Low Power SoCs. MTV Sankaran M. Menon, Ashish Gupta, Chinna Prudvi, Rolf Kühnis, Sukhbinder Singh Takhar, Spencer K. Millican, Eric Rentschler, Pandy Kalimuthu, Preeti Ranjan Panda, Priyadarsan Patra
2017	J	`jnl`	Selected Articles from the IEEE ISED 2016 Conference. J. Low Power Electron. Jimson Mathew, Hafizur Rahaman, Priyadarsan Patra, Dhiraj K. Pradhan
2015	—	`conf`	Fabrics on Die: Where Function, Debug and Test Meet. NOCS Priyadarsan Patra, Chinna Prudvi
2015	J	`jnl`	Selected Articles from the IEEE ISED 2014 Conference. J. Low Power Electron. Jimson Mathew, Hafizur Rahaman, Priyadarsan Patra, Dhiraj K. Pradhan
2014	J	`jnl`	Selected Articles from the IEEE ISED 2013 Conference. J. Low Power Electron. Jimson Mathew, A. Prasad Vinod, Priyadarsan Patra
2013	—	`conf`	Double Layer Perceptron Synchronized Computational Intelligence Guided Fractal Triangle Based Cryptographic Technique for Secured Communication (DLPFT). ISED Arindam Sarkar, J. K. Mandal, Priyadarsan Patra
2013	—	`conf`	Dynamic Selection of Trace Signals for Post-Silicon Debug. MTV Kanad Basu, Prabhat Mishra, Priyadarsan Patra, Amir Nahir, Allon Adir
2013	Misc	`conf`	Observability-aware Directed Test Generation for Soft Errors and Crosstalk Faults. VLSI Design Kanad Basu, Prabhat Mishra, Priyadarsan Patra
2013	J	`jnl`	Selected Articles from the IEEE ISED 2012 Conference. J. Low Power Electron. Jimson Mathew, Priyadarsan Patra
2012	—	`conf`	Constrained signal selection for post-silicon validation. HLDVT Kanad Basu, Prabhat Mishra, Priyadarsan Patra
2011	—	`conf`	Bee Colony Inspired Metamodeling Based Fast Optimization of a Nano-CMOS PLL. ISED Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos, Priyadarsan Patra
2011	A	`conf`	Efficient combination of trace and scan signals for post silicon validation and debug. ITC Kanad Basu, Prabhat Mishra, Priyadarsan Patra
2009	—	`conf`	A PVT aware accurate statistical logic library for high- metal-gate nano-CMOS. ISQED Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos, Priyadarsan Patra
2008	—	`conf`	Impact of Process and Temperature Variations on Network-on-Chip Design Exploration. NOCS Bin Li, Li-Shiuan Peh, Priyadarsan Patra
2008	—	`conf`	Runtime Validation of Transactional Memory Systems. ISQED Kaiyu Chen, Sharad Malik, Priyadarsan Patra
2008	A*	`conf`	Runtime validation of memory ordering using constraint graph checking. HPCA Kaiyu Chen, Sharad Malik, Priyadarsan Patra
2007	J	`jnl`	On the cusp of a validation wall. IEEE Des. Test Comput. Priyadarsan Patra
2003	A	`conf`	ESTIMA: an architectural-level power estimator for multi-ported pipelined register files. ISLPED Kavel M. Büyüksahin, Priyadarsan Patra, Farid N. Najm
2002	C	`conf`	A System-Level Solution to Domino Synthesis with 2 GHz Application. ICCD B. Chappell, Xinning Wang, Priyadarsan Patra, Prashant Saxena, J. Vendrell, Satyanarayan Gupta, S. Varadarajan, W. Gomes, S. Hussain, H. Krishnamurthy, M. Venkateshmurthy, S. Jain
1997	—	`conf`	Delay Insensitive Logic for RSFQ Superconductor Technology. ASYNC Priyadarsan Patra, Stanislav Polonsky, Donald S. Fussell
1996	C	`conf`	Efficient Delay-Insensitive RSFQ Circuits. ICCD Priyadarsan Patra, Donald S. Fussell
1995	Misc	`conf`	Fully asynchronous, robust, high-throughput arithmetic structures. VLSI Design Priyadarsan Patra, Donald S. Fussell
1995	—	`conf`	Power-efficient delay-insensitive codes for data transmission. HICSS (1) Priyadarsan Patra, Donald S. Fussell
1994	—	`conf`	Efficient building blocks for delay insensitive circuits. ASYNC Priyadarsan Patra, Donald S. Fussell