Pritish Narayanan

54 papers A* 1C 6Journal 20Unranked 27

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Analog AI Accelerators for Transformer-based Language Models: Hardware, Workload, and Power Performance. IMW H. Tsai, Hadjer Benmeziane, Irem Boybat, Julian Büchel, Pritish Narayanan, Manuel Le Gallo, S. Jain, Athanasios Vasilopoulos, W. Simon, Kohji Hosokawa, M. Ishii, Yasuteru Kohda, A. Chen, Charles Mackin, Kaoutar El Maghraoui, Atsuya Okazaki, Alexander M. Friz, Jose Luquin, Abu Sebastian, V. Narayanan, Geoffrey W. Burr
2025	—	`conf`	Analog-AI Hardware Accelerators for Low-Latency Transformer-Based Language Models (Invited). CICC Geoffrey W. Burr, H. Tsai, Irem Boybat, William Andrew Simon, Julian Büchel, Athanasios Vasilopoulos, Pritish Narayanan, Andrea Fasoli, Kohji Hosokawa, Manuel Le Gallo, M. Ishii, Yasuteru Kohda, Atsuya Okazaki, A. Chen, Charles Mackin, Elena Ferro, Kaoutar El Maghraoui, Hadjer Benmeziane, T. Philicelli, Corey Lammie, Alexander M. Friz, Jose Luquin, S. Jain, Abu Sebastian, V. Narayanan
2025	J	`jnl`	Rapid yet accurate Tile-circuit and device modeling for Analog In-Memory Computing. CoRR Jose Luquin, Charles Mackin, Stefano Ambrogio, An Chen, F. Baldi, G. Miralles, Malte J. Rasch, Julian Büchel, M. Lalwani, W. Ponghiran, Paul Solomon, Hsinyu Tsai, Geoffrey W. Burr, Pritish Narayanan
2023	J	`jnl`	A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh. IEEE Trans. Very Large Scale Integr. Syst. Shubham Jain, Hsinyu Tsai, Ching-Tzu Chen, Ramachandran Muralidhar, Irem Boybat, Martin M. Frank, Stanislaw Wozniak, Milos Stanisavljevic, Praneet Adusumilli, Pritish Narayanan, Kohji Hosokawa, Masatoshi Ishii, Arvind Kumar, Vijay Narayanan, Geoffrey W. Burr
2023	J	`jnl`	An analog-AI chip for energy-efficient speech recognition and transcription. Nat. Stefano Ambrogio, Pritish Narayanan, Atsuya Okazaki, Andrea Fasoli, Charles Mackin, Kohji Hosokawa, Akiyo Nomura, Takeo Yasuda, An Chen, Alexander M. Friz, Masatoshi Ishii, Jose Luquin, Yasuteru Kohda, Nicole Saulnier, Kevin Brew, Samuel Choi, Injo Ok, Timothy Philip, Victor Chan, Mary Claire Silvestre, Ishtiaq Ahsan, Vijay Narayanan, Hsinyu Tsai, Geoffrey W. Burr
2023	C	`conf`	Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited). ISCAS Hsinyu Tsai, Pritish Narayanan, Shubham Jain, Stefano Ambrogio, Kohji Hosokawa, Masatoshi Ishii, Charles Mackin, Ching-Tzu Chen, Atsuya Okazaki, Akiyo Nomura, Irem Boybat, Ramachandran Muralidhar, Martin M. Frank, Takeo Yasuda, Alexander M. Friz, Yasuteru Kohda, An Chen, Andrea Fasoli, Malte J. Rasch, Stanislaw Wozniak, Jose Luquin, Vijay Narayanan, Geoffrey W. Burr
2023	J	`jnl`	Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators. CoRR Malte J. Rasch, Charles Mackin, Manuel Le Gallo, An Chen, Andrea Fasoli, Frédéric Odermatt, Ning Li, S. R. Nandakumar, Pritish Narayanan, Hsinyu Tsai, Geoffrey W. Burr, Abu Sebastian, Vijay Narayanan
2023	—	`conf`	Impact of Phase-Change Memory Drift on Energy Efficiency and Accuracy of Analog Compute-in-Memory Deep Learning Inference (Invited). IRPS Martin M. Frank, Ning Li, Malte J. Rasch, Shubham Jain, Ching-Tzu Chen, Ramachandran Muralidhar, Jin-Ping Han, Vijay Narayanan, Timothy Philip, Kevin Brew, Andrew Simon, Iqbal Saraf, Nicole Saulnier, Irem Boybat, Stanislaw Wozniak, Abu Sebastian, Pritish Narayanan, Charles Mackin, An Chen, Hsinyu Tsai, Geoffrey W. Burr
2023	—	`conf`	Phase Change Memory-based Hardware Accelerators for Deep Neural Networks (invited). VLSI Technology and Circuits Geoffrey W. Burr, Pritish Narayanan, Stefano Ambrogio, Atsuya Okazaki, Hsinyu Tsai, Kohji Hosokawa, Charles Mackin, Akiyo Nomura, Takeo Yasuda, J. Demarest, Kevin Brew, Victor Chan, Samuel Choi, T. Gordon, T. M. Levin, Alexander M. Friz, Masatoshi Ishii, Yasuteru Kohda, An Chen, Andrea Fasoli, Jose Luquin, Nicole Saulnier, S. Teehan, Ishtiaq Ahsan, Vijay Narayanan
2022	C	`conf`	Analog-memory-based 14nm Hardware Accelerator for Dense Deep Neural Networks including Transformers. ISCAS Atsuya Okazaki, Pritish Narayanan, Stefano Ambrogio, Kohji Hosokawa, Hsinyu Tsai, Akiyo Nomura, Takeo Yasuda, Charles Mackin, Alexander M. Friz, Masatoshi Ishii, Yasuteru Kohda, Katie Spoon, An Chen, Andrea Fasoli, Malte J. Rasch, Geoffrey W. Burr
2021	C	`conf`	Circuit Techniques for Efficient Acceleration of Deep Neural Network Inference with Analog-AI (Invited). ISCAS Kohji Hosokawa, Pritish Narayanan, Stefano Ambrogio, Hsinyu Tsai, Charles Mackin, Andrea Fasoli, Alexander M. Friz, An Chen, Jose Luquin, Katherine Spoon, Geoffrey W. Burr, Scott C. Lewis
2021	J	`jnl`	Toward Software-Equivalent Accuracy on Transformer-Based Deep Neural Networks With Analog Memory Devices. Frontiers Comput. Neurosci. Katie Spoon, Hsinyu Tsai, An Chen, Malte J. Rasch, Stefano Ambrogio, Charles Mackin, Andrea Fasoli, Alexander M. Friz, Pritish Narayanan, Milos Stanisavljevic, Geoffrey W. Burr
2020	—	`conf`	Accelerating Deep Neural Networks with Analog Memory Devices. AICAS Stefano Ambrogio, Pritish Narayanan, Hsinyu Tsai, Charles Mackin, Katherine Spoon, An Chen, Andrea Fasoli, Alexander M. Friz, Geoffrey W. Burr
2020	—	`conf`	Neuromorphic Computing with Phase Change, Device Reliability, and Variability Challenges. IRPS Charles Mackin, Pritish Narayanan, Stefano Ambrogio, Hsinyu Tsai, Katie Spoon, Andrea Fasoli, An Chen, Alexander M. Friz, Robert M. Shelby, Geoffrey W. Burr
2020	C	`conf`	Optimization of Analog Accelerators for Deep Neural Networks Inference. ISCAS Andrea Fasoli, Stefano Ambrogio, Pritish Narayanan, Hsinyu Tsai, Charles Mackin, Katherine Spoon, Alexander M. Friz, An Chen, Geoffrey W. Burr
2020	J	`jnl`	Overview of the IBM Neural Computer Architecture. CoRR Pritish Narayanan, Charles E. Cox, Alexis Asseman, Nicolas Antoine, Harald Huels, Winfried W. Wilcke, Ahmet S. Ozcan
2019	J	`jnl`	AI hardware acceleration with analog memory: Microarchitectures for low energy at high speed. IBM J. Res. Dev. Hung-Yang Chang, Pritish Narayanan, Scott C. Lewis, Nathan C. P. Farinha, Kohji Hosokawa, Charles Mackin, Hsinyu Tsai, Stefano Ambrogio, An Chen, Geoffrey W. Burr
2019	J	`jnl`	Analog-to-Digital Conversion With Reconfigurable Function Mapping for Neural Networks Activation Function Acceleration. IEEE J. Emerg. Sel. Topics Circuits Syst. Massimo Giordano, Giorgio Cristiano, Koji Ishibashi, Stefano Ambrogio, Hsinyu Tsai, Geoffrey W. Burr, Pritish Narayanan
2019	—	`conf`	Non-filamentary non-volatile memory elements as synapses in neuromorphic systems. NVMTS Alessandro Fumarola, Yusuf Leblebici, Pritish Narayanan, Robert M. Shelby, L. L. Sanchez, Geoffrey W. Burr, Kibong Moon, J. Jang, Hyunsang Hwang, Severin Sidler
2018	J	`jnl`	Equivalent-accuracy accelerated neural-network training using analogue memory. Nat. Stefano Ambrogio, Pritish Narayanan, Hsinyu Tsai, Robert M. Shelby, Irem Boybat, Carmelo di Nolfo, Severin Sidler, Massimo Giordano, Martina Bodini, Nathan C. P. Farinha, Benjamin Killeen, Christina Cheng, Yassine Jaoudi, Geoffrey W. Burr
2018	—	`conf`	Panel discussions: "Challenges to the scaling limits: How can we achieve sustainable power-performance improvements?". COOL CHIPS Koji Inoue, Takuya Araki, Takumi Maruyama, Pritish Narayanan, Takashi Oshima, Martin Schulz
2017	—	`conf`	Improved Deep Neural Network Hardware-Accelerators Based on Non-Volatile-Memory: The Local Gains Technique. ICRC Irem Boybat, Carmelo di Nolfo, Stefano Ambrogio, Martina Bodini, Nathan C. P. Farinha, Robert M. Shelby, Pritish Narayanan, Severin Sidler, Hsinyu Tsai, Yusuf Leblebici, Geoffrey W. Burr
2017	C	`conf`	Neuromorphic devices and architectures for next-generation cognitive computing. ISCAS Geoffrey W. Burr, Pritish Narayanan, Robert M. Shelby, Stefano Ambrogio, Hsinyu Tsai, Scott L. Lewis, Kohji Hosokawa
2017	C	`conf`	Reducing circuit design complexity for neuromorphic machine learning systems based on Non-Volatile Memory arrays. ISCAS Pritish Narayanan, Lucas L. Sanches, Alessandro Fumarola, Robert M. Shelby, Stefano Ambrogio, Jun-Woo Jang, Hyunsang Hwang, Yusuf Leblebici, Geoffrey W. Burr
2017	J	`jnl`	Toward on-chip acceleration of the backpropagation algorithm using nonvolatile memory. IBM J. Res. Dev. Pritish Narayanan, Alessandro Fumarola, Lucas L. Sanches, Kohji Hosokawa, Scott C. Lewis, Robert M. Shelby, Geoffrey W. Burr
2016	—	`conf`	Accelerating machine learning with Non-Volatile Memory: Exploring device and circuit tradeoffs. ICRC Alessandro Fumarola, Pritish Narayanan, Lucas L. Sanches, Severin Sidler, Jun-Woo Jang, Kibong Moon, Robert M. Shelby, Hyunsang Hwang, Geoffrey W. Burr
2016	J	`jnl`	Circuit-Level Benchmarking of Access Devices for Resistive Nonvolatile Memory Arrays. IEEE J. Emerg. Sel. Topics Circuits Syst. Pritish Narayanan, Geoffrey W. Burr, Kumar Virwani, Bülent N. Kurdi
2016	—	`conf`	Large-scale neural networks implemented with Non-Volatile Memory as the synaptic weight element: Impact of conductance response. ESSDERC Severin Sidler, Irem Boybat, Robert M. Shelby, Pritish Narayanan, Jun-Woo Jang, Alessandro Fumarola, Kibong Moon, Yusuf Leblebici, Hyunsang Hwang, Geoffrey W. Burr
2015	A*	`conf`	Deep Learning with Limited Numerical Precision. ICML Suyog Gupta, Ankur Agrawal, Kailash Gopalakrishnan, Pritish Narayanan
2015	J	`jnl`	Deep Learning with Limited Numerical Precision. CoRR Suyog Gupta, Ankur Agrawal, Kailash Gopalakrishnan, Pritish Narayanan
2014	J	`jnl`	Introduction to JPDC special issue on computing with future nanotechnology. J. Parallel Distributed Comput. Csaba Andras Moritz, Santosh Khasanvis, Pritish Narayanan
2014	J	`jnl`	Metal-Gated Junctionless Nanowire Transistors. CoRR Mostafizur Rahman, Pritish Narayanan, Csaba Andras Moritz
2014	J	`jnl`	Parameter variation sensing and estimation in nanoscale fabrics. J. Parallel Distributed Comput. Jianfeng Zhang, Mostafizur Rahman, Pritish Narayanan, Santosh Khasanvis, Csaba Andras Moritz
2013	—	`conf`	Experimental prototyping of beyond-CMOS nanowire computing fabrics. NANOARCH Mostafizur Rahman, Pritish Narayanan, Santosh Khasanvis, John Nicholson, Csaba Andras Moritz
2013	—	`conf`	Nanowire field-programmable computing platform. NANOARCH Santosh Khasanvis, Mostafizur Rahman, Prasad Shabadi, Pritish Narayanan, Hyung Suk Yu, Chi On Chui, Csaba Andras Moritz
2013	J	`jnl`	Variability in Nanoscale Fabrics: Bottom-up Integrated Analysis and Mitigation. ACM J. Emerg. Technol. Comput. Syst. Pritish Narayanan, Michael Leuchtenburg, Jorge Kina, Prachi Joshi, Pavan Panchapakeshan, Chi On Chui, Csaba Andras Moritz
2012	—	`conf`	Ternary volatile random access memory based on heterogeneous graphene-CMOS fabric. NANOARCH Santosh Khasanvis, K. M. Masum Habib, Mostafizur Rahman, Pritish Narayanan, Roger K. Lake, Csaba Andras Moritz
2011	—	`conf`	Biased Voting for Improved Yield in Nanoscale Fabrics. DFT Md. Muwyid U. Khan, Pritish Narayanan, Priyamvada Vijayakumar, Israel Koren, C. Mani Krishna, Csaba Andras Moritz
2011	J	`jnl`	Energy-Efficient Hardware Data Prefetching. IEEE Trans. Very Large Scale Integr. Syst. Yao Guo, Pritish Narayanan, Mahmoud A. Bennaser, Saurabh Chheda, Csaba Andras Moritz
2011	—	`conf`	Hybrid Graphene Nanoribbon-CMOS tunneling volatile memory fabric. NANOARCH Santosh Khasanvis, K. M. Masum Habib, Mostafizur Rahman, Pritish Narayanan, Roger K. Lake, Csaba Andras Moritz
2011	—	`conf`	Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics. NANOARCH Priyamvada Vijayakumar, Pritish Narayanan, Israel Koren, C. Mani Krishna, Csaba Andras Moritz
2011	—	`conf`	N3ASICs: Designing nanofabrics with fine-grained CMOS integration. NANOARCH Pavan Panchapakeshan, Pritish Narayanan, Csaba Andras Moritz
2011	—	`conf`	Nanoscale Application Specific Integrated Circuits. NANOARCH Pritish Narayanan, Jorge Kina, Pavan Panchapakeshan, Priyamvada Vijayakumar, Kyeong-Sik Shin, Mostafizur Rahman, Michael Leuchtenburg, Israel Koren, Chi On Chui, Csaba Andras Moritz
2011	—	`conf`	Regular 2D NASIC-based architecture and design space exploration. NANOARCH Ciprian Teodorov, Pritish Narayanan, Loïc Lagadec, Catherine Dezan
2010	—	`conf`	Incorporating Heterogeneous Redundancy in a Nanoprocessor for Improved Yield and Performance. DFT Priyamvada Vijayakumar, Pritish Narayanan, Israel Koren, C. Mani Krishna, Csaba Andras Moritz
2010	—	`conf`	Parameter Variability in Nanoscale Fabrics: Bottom-Up Integrated Exploration. DFT Pritish Narayanan, Michael Leuchtenburg, Jorge Kina, Prachi Joshi, Pavan Panchapakeshan, Chi On Chui, Csaba Andras Moritz
2010	J	`jnl`	Programmable cellular architectures at the nanoscale. Nano Commun. Networks Pritish Narayanan, Teng Wang, Csaba Andras Moritz
2010	—	`conf`	Towards logic functions as the device. NANOARCH Prasad Shabadi, Alexander Khitun, Pritish Narayanan, Mingqiang Bao, Israel Koren, Kang L. Wang, Csaba Andras Moritz
2009	J	`jnl`	Towards a framework for designing applications onto hybrid nano/CMOS fabrics. Microelectron. J. Catherine Dezan, Ciprian Teodorov, Loïc Lagadec, Michael Leuchtenburg, Teng Wang, Pritish Narayanan, Csaba Andras Moritz
2009	—	`conf`	Validating cascading of crossbar circuits with an integrated device-circuit exploration. NANOARCH Pritish Narayanan, Csaba Andras Moritz, Kyoung-won Park, Chi On Chui
2008	—	`conf`	CMOS Control Enabled Single-Type FET NASIC. ISVLSI Pritish Narayanan, Michael Leuchtenburg, Teng Wang, Csaba Andras Moritz
2008	—	`conf`	Impact of Process Variation in Fault-Resilient Streaming Nanoprocessors. NanoNet Michael Leuchtenburg, Pritish Narayanan, Teng Wang, Csaba Andras Moritz
2007	—	`conf`	Combining 2-level logic families in grid-based nanoscale fabrics. NANOARCH Teng Wang, Pritish Narayanan, Csaba Andras Moritz
2007	J	`jnl`	Fault-Tolerant Nanoscale Processors on Semiconductor Nanowire Grids. IEEE Trans. Circuits Syst. I Regul. Pap. Csaba Andras Moritz, Teng Wang, Pritish Narayanan, Michael Leuchtenburg, Yao Guo, Catherine Dezan, Mahmoud A. Bennaser