Pritha Banerjee

17 papers A* 1B 1C 3Misc 4Journal 6Unranked 2
YearRankTypeTitle / Venue / Authors
2025 Misc conf
Constructing Rectilinear Steiner Minimum Tree with Conditional Generative Adversarial Network.
VLSID
Kritanta Saha, Pritha Banerjee, Susmita Sur-Kolay
2023 J jnl
Concurrent Steiner Tree Selection for Global routing with EUVL Flare Reduction.
Integr.
Sudipta Paul, Tridib Mukherjee, Pritha Banerjee, Susmita Sur-Kolay
2022 C conf
Stitch-avoiding Detailed Routing for Multiple E-Beam Lithography.
VLSI-SoC
Kritanta Saha, Pritha Banerjee, Susmita Sur-Kolay
2022 Misc conf
Stitch-avoiding Global Routing for Multiple E-Beam Lithography.
VLSID
Kritanta Saha, Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay
2021 J jnl
A study on flare minimisation in EUV lithography by post-layout re-allocation of wire segments.
IET Circuits Devices Syst.
Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay
2019 — conf
Minimization of Flare in EUVL by Simultaneous Wire Segment Perturbation and Dummification.
ISVLSI
Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay
2017 C conf
Post-Layout Perturbation towards Stitch Friendly Layout for Multiple E-Beam Lithography.
ICCD
Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay
2015 C conf
Flare reduction in EUV Lithography by perturbation of wire segments.
VLSI-SoC
Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay
2013 A* conf
An efficient and effective analytical placer for FPGAs.
DAC
Tzu-Hen Lin, Pritha Banerjee, Yao-Wen Chang
2011 J jnl
Cone-based placement for field programmable gate arrays.
IET Comput. Digit. Tech.
Pritha Banerjee, Debasri Saha, Susmita Sur-Kolay
2011 J jnl
Floorplanning for Partially Reconfigurable FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay
2009 J jnl
FPGA placement using space-filling curves: Theory meets practice.
ACM Trans. Embed. Comput. Syst.
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu, Sandip Das, Subhas C. Nandy, Subhasis Bhattacharjee
2009 J jnl
Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu
2009 Misc conf
Floorplanning for Partial Reconfiguration in FPGAs.
VLSI Design
Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay
2007 — conf
Faster Placer for Island-Style FPGAs.
ICCTA
Pritha Banerjee, Susmita Sur-Kolay
2007 Misc conf
Floorplanning in Modern FPGAs.
VLSI Design
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu
2005 B conf
Fast FPGA Placement using Space-filling Curve.
FPL
Pritha Banerjee, Subhasis Bhattacharjee, Susmita Sur-Kolay, Sandip Das, Subhas C. Nandy