Pritam Bhattacharjee

15 papers Misc 1Journal 7Unranked 7
YearRankTypeTitle / Venue / Authors
2024 — conf
A Method of Variable Frequency Clock Generation.
iSES
Vipin Kumar Singh, Vijay Pratap Yadav, Tika Ram Pokhrel, Pritam Bhattacharjee, Alak Majumder
2024 — conf
An Algorithmic Approach of Generating a VFC of Low Average Frequency Ramp.
iSES
Priyanka J, Ankita Deb, Pritam Bhattacharjee, Alak Majumder
2024 Misc conf
Design of VFC with Programmable Frequency Ramp to control on-chip switching current profile.
VLSID
Pritam Bhattacharjee, Alak Majumder
2024 — conf
Exploring the Application of Variable Frequency Clock as the Constituent of OCT.
iSES
Priyanka J, Pritam Bhattacharjee, Alak Majumder
2023 — conf
Comparative Exploration of Gate Count and Leakage Optimized D-Latch in Nanometer CMOS.
RADIOELEKTRONIKA
Pritam Bhattacharjee, G. Naveen Goud, Vipin Kumar Singh, Vijay Pratap Yadav, Abir J. Mondal, Alak Majumder
2022 J jnl
Clock-Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pritam Bhattacharjee, Prerna Rana, Bidyut K. Bhattacharyya, Alak Majumder
2021 J jnl
A Vector-Controlled Variable Delay Circuit to Develop Near-Symmetric Output Rise/Fall Time.
Circuits Syst. Signal Process.
Pritam Bhattacharjee, Bidyut K. Bhattacharyya, Alak Majumder
2019 J jnl
A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application.
J. Circuits Syst. Comput.
Pritam Bhattacharjee, Alak Majumder
2018 J jnl
A Novel Gating Approach to Alleviate Power and Ground Noise in Silicon Chips.
J. Circuits Syst. Comput.
Alak Majumder, Pritam Bhattacharjee, Tushar Dhabal Das
2018 J jnl
Data-Dependent Clock Gating approach for Low Power Sequential System.
CoRR
Dhiraj Sarkar, Pritam Bhattacharjee, Alak Majumder
2018 J jnl
LECTOR Based Clock Gating for Low Power Multi-Stage Flip Flop Applications.
CoRR
Pritam Bhattacharjee, Bipasha Nath, Alak Majumder
2017 — conf
Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip.
iNIS
Alak Majumder, Pritam Bhattacharjee
2017 J jnl
Estimation of Power Dissipation in Ternary Quantum Dot Cellular Automata Cell.
J. Low Power Electron.
Pritam Bhattacharjee, Kunal Das, Arijit Dey, Debashis De, Swarnendu Kumar Chakraborty
2016 — conf
A 90 nm leakage control transistor based clock gating for low power flip flop applications.
MWSCAS
Pritam Bhattacharjee, Alak Majumder, Tushar Dhabal Das
2016 — conf
LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder.
iNIS
Pritam Bhattacharjee, Alak Majumder