Prerna Budhkar

14 papers A 2B 1C 1Journal 4Unranked 5
YearRankTypeTitle / Venue / Authors
2026 J jnl
A Standardized 20-Tb/s Bandwidth Scalable Heterogeneous 2.5-D System Supporting Assembly Time Workload-Dependent Chiplet Configurations.
IEEE J. Solid State Circuits
Srivatsa Rangachar Srinivasa, Dileep John Kurian, Paolo A. Aseron, Prerna Budhkar, Vinayak Honkote, Dan Lake, Mikhail J. Moiseev, Robert J. Munoz, Anuradha Srinivasan, Tanay Karnik
2025 — conf
A 300MB SRAM, 20Tb/s Bandwidth Scalable Heterogenous 2.5D System Inferencing Simultaneous Streams Across 20 Chiplets with Workload-Dependent Configurations.
ISSCC
Srivatsa Rangachar Srinivasa, Dileep Kurian, Paolo A. Aseron, Prerna Budhkar, Arun Radhakrishnan, Alejandro Cardenas Lopez, Jainaveen Sundaram, Vinayak Honkote, Leonid Azarenkov, Dan Lake, Jaykant Timbadiya, Mikhail J. Moiseev, Brando Perez Esparza, Ronald Kalim, Erika Ramirez Lozano, Mukesh Bhartiya, Sriram Muthukumar, Satish Yada, Sureshbabu Kadavakollu, Saransh Chhabra, Kamakhya Prasad Sahu, James Greensky, Xavier Brun, Esdras Juarez Hernandez, Robert Munoz, Thomas P. Thomas, Shawna Liff, Vivek De, Anuradha Srinivasan, Tanay Karnik
2025 — conf
A 68 TOPS/W, 256MB SRAM Sparse GEMM Accelerator Tiled Across 16, 4nm Near Memory Compute (NMC) Chiplets Disaggregated 2.5D System.
CICC
Srivatsa Rangachar Srinivasa, Prerna Budhkar, Gauthaman Murali, Vui Seng Chua, Paolo A. Aseron, Vinayak Honkote, Ravi R. Iyer, Nilesh Jain, Dileep John Kurian, Anuradha Srinivasan, Tanay Karnik
2025 — conf
A High-Performance Passive Base System for Distributed AI/Media Acceleration.
CICC
Ragh Kuttappa, Jainaveen Sundaram, Srivatsa Rangachar Srinivasa, Paolo A. Aseron, Gauthaman Murali, Vinayak Honkote, Prerna Budhkar, Dileep Kurian, Ronald Kalim, Thomas P. Thomas, Anuradha Srinivasan, Tanay Karnik
2025 A conf
Invited Paper: System and Technology Co-Optimization Framework for a Disaggregated System with Passive Die 2.5D Integration.
ICCAD
Gauthaman Murali, Mudit Bhargava, Shairfe Salahuddin, Zhichao Chen, Archana Pandey, Srivatsa Rangachar Srinivasa, Prerna Budhkar, Ragh Kuttappa, Vinayak Honkote, Prashanth Sakthi, Myung-Hee Na, Tanay Karnik
2025 — conf
System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution.
ACM Great Lakes Symposium on VLSI
Srivatsa Rangachar Srinivasa, Dileep Kurian, Paolo A. Aseron, Prerna Budhkar, Vinayak Honkote, Dan Lake, Jaykant Timbadiya, Satish Yada, Suresh Kadavakollu, James Greensky, Gauthaman Murali, Anuradha Srinivasan, Ragh Kuttappa, Tanay Karnik
2023 B conf
CPU Microarchitectural Performance Analysis of SVT-AV1 Encoder.
ICIP
Prerna Budhkar, Navneet Rao, Jainaveen Sundaram, Tanay Karnik
2021 J jnl
Efficient local locking for massively multithreaded in-memory hash-based operators.
VLDB J.
Bashar Romanous, Skyler Windh, Ildar Absalyamov, Prerna Budhkar, Robert J. Halstead, Walid A. Najjar, Vassilis J. Tsotras
2019 J jnl
Accelerating In-Memory Database Selections Using Latency Masking Hardware Threads.
ACM Trans. Archit. Code Optim.
Prerna Budhkar, Ildar Absalyamov, Vasileios Zois, Skyler Windh, Walid A. Najjar, Vassilis J. Tsotras
2019 — conf
Scalable Low-Latency Persistent Neural Machine Translation on CPU Server with Multiple FPGAs.
FPT
Eriko Nurvitadhi, Mishali Naik, Andrew Boutros, Prerna Budhkar, Ali Jafari, Dongup Kwon, David Sheffield, Abirami Prabhakaran, Karthik Gururaj, Pranavi Appana
2018 — —
Accelerating Irregular Applications Using Latency Masking Multithreaded Techniques.
Prerna Budhkar
2016 C conf
FPGA-accelerated group-by aggregation using synchronizing caches.
DaMoN
Ildar Absalyamov, Prerna Budhkar, Skyler Windh, Robert J. Halstead, Walid A. Najjar, Vassilis J. Tsotras
2015 A conf
CAMs as Synchronizing Caches for Multithreaded Irregular Applications on FPGAs.
ICCAD
Skyler Windh, Prerna Budhkar, Walid A. Najjar
2015 J jnl
High-Level Language Tools for Reconfigurable Computing.
Proc. IEEE
Skyler Windh, Xiaoyin Ma, Robert J. Halstead, Prerna Budhkar, Zabdiel Luna, Omar Hussaini, Walid A. Najjar