Premachandran R. Menon

42 papers A 13C 2Misc 3Journal 22Unranked 2

Year	Rank	Type	Title / Venue / Authors
2006	J	`jnl`	Design-specific path delay testing in lookup-table-based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Premachandran R. Menon, Weifeng Xu, Russell Tessier
2001	A	`conf`	BIST-based delay path testing in FPGA architectures. ITC Ian G. Harris, Premachandran R. Menon, Russell Tessier
2001	J	`jnl`	Identification of primitive faults in combinational and sequentialcircuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ramesh C. Tekumalla, Premachandran R. Menon
2000	J	`jnl`	On Redundant Path Delay Faults in Synchronous Sequential Circuits. IEEE Trans. Computers Ramesh C. Tekumalla, Premachandran R. Menon
1999	A	`conf`	Robust testability of primitive faults using test points. ITC Ramesh C. Tekumalla, Premachandran R. Menon
1998	A	`conf`	On primitive fault test generation in non-scan sequential circuits. ICCAD Ramesh C. Tekumalla, Premachandran R. Menon
1997	A	`conf`	Delay Testing with Clock Control: An Alternative to Enhanced Scan. ITC Ramesh C. Tekumalla, Premachandran R. Menon
1997	C	`conf`	Synthesis of Delay Verifiable Sequential Circuits using Partial Enhanced Scan. ICCD Ramesh C. Tekumalla, Premachandran R. Menon
1997	A	`conf`	Test generation for primitive path delay faults in combinational circuits. ICCAD Ramesh C. Tekumalla, Premachandran R. Menon
1996	Misc	`conf`	Identifying Redundant Path Delay Faults in Sequential Circuits. VLSI Design Ramesh C. Tekumalla, Premachandran R. Menon
1995	J	`jnl`	Delay-testable implementations of symmetric functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wuudiann Ke, Premachandran R. Menon
1995	J	`jnl`	Multifault and delay-fault testability of multilevel circuits. J. Electron. Test. Wuudiann Ke, Premachandran R. Menon
1995	Misc	`conf`	Multifault testability of delay-testable circuits. VTS Wuudiann Ke, Premachandran R. Menon
1995	J	`jnl`	Path-delay-fault testable nonscan sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wuudiann Ke, Premachandran R. Menon
1995	J	`jnl`	Synthesis of Delay-Verifiable Combinational Circuits. IEEE Trans. Computers Wuudiann Ke, Premachandran R. Menon
1994	—	`conf`	Delay Reduction by Segment Substitution. EDAC-ETC-EUROASIC Hitesh Ajuha, Premachandran R. Menon
1994	C	`conf`	Delay-Verifiability of Combinational Circuits Based on Primitive Faults. ICCD Wuudiann Ke, Premachandran R. Menon
1994	Misc	`conf`	Realization of fully path-delay-fault testable non-scan sequential circuits. VTS Wuudiann Ke, Premachandran R. Menon
1994	—	`conf`	Synthesis of Delay-Verifiable Two-Level Circuits. EDAC-ETC-EUROASIC Wuudiann Ke, Premachandran R. Menon
1993	J	`jnl`	3-valued trace-based fault simulation of synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ohyoung Song, Premachandran R. Menon
1993	J	`jnl`	Acceleration of trace-based fault simulation of combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ohyoung Song, Premachandran R. Menon
1992	J	`jnl`	Stuck-open testable scan-based CMOS sequential circuits. IEEE J. Solid State Circuits Bong-Hee Park, Premachandran R. Menon
1991	A	`conf`	Robustly Scan-Testable CMOS Sequential Circuits. ITC Bong-Hee Park, Premachandran R. Menon
1991	J	`jnl`	SCRIPT: a critical path tracing algorithm for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Premachandran R. Menon, Ytzhak H. Levendel, Miron Abramovici
1990	A	`conf`	Design of scan-testable CMOS sequential circuits. ITC Bong-Hee Park, Premachandran R. Menon
1990	A	`conf`	Parallel pattern fault simulation based on stem faults in combinational circuits. ITC Ohyoung Song, Premachandran R. Menon
1989	A	`conf`	An Approach to Functional Level Testability Analysis. ITC C. H. Chen, Premachandran R. Menon
1989	A	`conf`	Symbolic Test Generation for Hierarchically Modeled Digital Systems. ITC P. N. Anirudhan, Premachandran R. Menon
1986	J	`jnl`	SMART and FAST: Test Generation for VLSI Scan-Design Circuits. IEEE Des. Test Miron Abramovici, James J. Kulikowski, Premachandran R. Menon, David T. Miller
1985	A	`conf`	Test Generation In Lamp2: Concepts and Algorithms. ITC Miron Abramovici, James J. Kulikowski, Premachandran R. Menon, David T. Miller
1985	A	`conf`	Test Generation In Lamp2: System Overview. ITC Miron Abramovici, James J. Kulikowski, Premachandran R. Menon, David T. Miller
1983	J	`jnl`	A Logic Simulation Machine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Miron Abramovici, Ytzhak H. Levendel, Premachandran R. Menon
1983	A	`conf`	A Practical Approach to Fault Simulation and Test Generation for Bridging Faults. ITC Miron Abramovici, Premachandran R. Menon
1983	J	`jnl`	Totally Preset Checking Experiments for Sequential Machines. IEEE Trans. Computers Gordon K. Lin, Premachandran R. Menon
1982	J	`jnl`	Test Generation Algorithms for Computer Hardware Description Languages. IEEE Trans. Computers Ytzhak H. Levendel, Premachandran R. Menon
1978	J	`jnl`	Deductive Fault Simulation with Functional Blocks. IEEE Trans. Computers Premachandran R. Menon, Stephen G. Chappell
1973	J	`jnl`	Restricted Checking Sequences for Sequential Machines. IEEE Trans. Computers Arthur D. Friedman, Premachandran R. Menon
1971	J	`jnl`	Fault Detection in Iterative Logic Arrays. IEEE Trans. Computers Premachandran R. Menon, Arthur D. Friedman
1969	J	`jnl`	Design of Asynchronous Circuits Assuming Unbounded Gate Delays. IEEE Trans. Computers Douglas B. Armstrong, Arthur D. Friedman, Premachandran R. Menon
1969	J	`jnl`	On Sequential Machine Decompositions for Reducing the Number of Delay Elements Inf. Control. Premachandran R. Menon
1969	J	`jnl`	Structural Simplification and Decomposition of Asynchronous Sequential Circuits. IEEE Trans. Computers Chung-Jen Tan, Premachandran R. Menon, Arthur D. Friedman
1968	J	`jnl`	Realization of Asynchronous Sequential Circuits Without Inserted Delay Elements. IEEE Trans. Computers Douglas B. Armstrong, Arthur D. Friedman, Premachandran R. Menon