Preeti Ranjan Panda

125 papers A* 4A 19B 1C 5Misc 25Journal 52Unranked 18
YearRankTypeTitle / Venue / Authors
2025 J jnl
Cryo-CACTI: Cryogenic-Aware CACTI for Cache Modeling Down to 10K in Advanced 7nm FinFETs.
IEEE Trans. Computers
Divya Praneetha Ravipati, Victor M. van Santen, Shivendra Singh Parihar, Yogesh Singh Chauhan, Preeti Ranjan Panda, Hussam Amrouch
2025 J jnl
FARRE: Fairness Aware Request Response Arbitration in Shared Caches.
ACM Trans. Embed. Comput. Syst.
Garima Modi, Priyanka Singla, Neetu Jindal, Ayan Mandal, Preeti Ranjan Panda
2025 J jnl
FLASH: Deadline-Aware Flexible LLC Arbitration and Scheduling for Hardware Accelerators.
ACM Trans. Embed. Comput. Syst.
Ayushi Agarwal, Pulkit Goel, P. J. Joseph, Prokash Ghosh, Sourav Roy, Preeti Ranjan Panda
2025 J jnl
SHARP: SHARing-Aware Cache Writeback byPass.
ACM Trans. Embed. Comput. Syst.
Dinesh Joshi, Aritra Bagchi, Preeti Ranjan Panda
2024 J jnl
3D-TemPo: Optimizing 3-D DRAM Performance Under Temperature and Power Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shailja Pandey, Sayam Sethi, Preeti Ranjan Panda
2024 C conf
APPAMM: Memory Management for IPsec Application on Heterogeneous SoCs.
VLSI-SoC
Ayushi Agarwal, Radhika Dharwadkar, Isaar Ahmad, Krishna Kumar, P. J. Joseph, Sourav Roy, Prokash Ghosh, Preeti Ranjan Panda
2024 — conf
Application-Aware Memory Management for IPsec on Heterogeneous SoCs.
VLSI-SoC (Selected Papers)
Ayushi Agarwal, Radhika Dharwadkar, Isaar Ahmad, Krishna Kumar, P. J. Joseph, Sourav Roy, Prokash Ghosh, Preeti Ranjan Panda
2024 J jnl
CAPE: Criticality-Aware Performance and Energy Optimization Policy for NCFET-Based Caches.
IEEE Trans. Computers
Divya Praneetha Ravipati, Ramanuj Goel, Victor M. van Santen, Hussam Amrouch, Preeti Ranjan Panda
2024 J jnl
COBRRA: COntention-aware cache Bypass with Request-Response Arbitration.
ACM Trans. Embed. Comput. Syst.
Aritra Bagchi, Dinesh Joshi, Preeti Ranjan Panda
2024 J jnl
NOVELLA: Nonvolatile Last-Level Cache Bypass for Optimizing Off-Chip Memory Energy.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Aritra Bagchi, Ohm Rishabh, Preeti Ranjan Panda
2024 J jnl
NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching.
ACM Trans. Design Autom. Electr. Syst.
Shailja Pandey, Lokesh Siddhu, Preeti Ranjan Panda
2024 J jnl
NeuroTAP: Thermal and Memory Access Pattern-Aware Data Mapping on 3D DRAM for Maximizing DNN Performance.
ACM Trans. Embed. Comput. Syst.
Shailja Pandey, Preeti Ranjan Panda
2024 J jnl
POEM: Performance Optimization and Endurance Management for Non-volatile Caches.
ACM Trans. Design Autom. Electr. Syst.
Aritra Bagchi, Dharamjeet, Ohm Rishabh, Manan Suri, Preeti Ranjan Panda
2023 J jnl
CABARRE: Request Response Arbitration for Shared Cache Management.
ACM Trans. Embed. Comput. Syst.
Garima Modi, Aritra Bagchi, Neetu Jindal, Ayan Mandal, Preeti Ranjan Panda
2023 J jnl
Dynamic Thermal Management of 3D Memory through Rotating Low Power States and Partial Channel Closure.
ACM Trans. Embed. Comput. Syst.
Lokesh Siddhu, Aritra Bagchi, Rajesh Kedia, Isaar Ahmad, Shailja Pandey, Preeti Ranjan Panda
2023 J jnl
Editorial.
IEEE Embed. Syst. Lett.
Preeti Ranjan Panda
2023 Misc conf
Education Abstract: Thermal Challenges and Mitigation in 3D DRAM.
CODES+ISSS
Preeti Ranjan Panda, Shailja Pandey
2023 J jnl
Performance and Energy Studies on NC-FinFET Cache-Based Systems With FN-McPAT.
IEEE Trans. Very Large Scale Integr. Syst.
Divya Praneetha Ravipati, Victor M. van Santen, Sami Salamin, Hussam Amrouch, Preeti Ranjan Panda
2022 J jnl
CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems.
ACM Trans. Archit. Code Optim.
Lokesh Siddhu, Rajesh Kedia, Shailja Pandey, Martin Rapp, Anuj Pathania, Jörg Henkel, Preeti Ranjan Panda
2022 A conf
CoreMemDTM: Integrated Processor Core and 3D Memory Dynamic Thermal Management for Improved Performance.
DATE
Lokesh Siddhu, Rajesh Kedia, Preeti Ranjan Panda
2022 J jnl
Editorial.
IEEE Embed. Syst. Lett.
Preeti Ranjan Panda
2022 J jnl
FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies.
IEEE Trans. Very Large Scale Integr. Syst.
Divya Praneetha Ravipati, Rajesh Kedia, Victor M. van Santen, Jörg Henkel, Preeti Ranjan Panda, Hussam Amrouch
2022 J jnl
NeuroMap: Efficient Task Mapping of Deep Neural Networks for Dynamic Thermal Management in High-Bandwidth Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shailja Pandey, Preeti Ranjan Panda
2021 J jnl
A Survey of Cache Simulators.
ACM Comput. Surv.
Hadi Brais, Rajshekar Kalayappan, Preeti Ranjan Panda
2021 Misc ed.
CASES '21: Proceedings of the 2021 International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, Virtual Event, October 8 - 15, 2021
CASES
Ümit Y. Ogras, Preeti Ranjan Panda
2021 J jnl
CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems.
CoRR
Lokesh Siddhu, Rajesh Kedia, Shailja Pandey, Martin Rapp, Anuj Pathania, Jörg Henkel, Preeti Ranjan Panda
2021 J jnl
Leakage-Aware Dynamic Thermal Management of 3D Memories.
ACM Trans. Design Autom. Electr. Syst.
Lokesh Siddhu, Rajesh Kedia, Preeti Ranjan Panda
2020 J jnl
Editorial-December 2020.
IEEE Embed. Syst. Lett.
Preeti Ranjan Panda
2020 J jnl
Enhancing Network-on-Chip Performance by Reusing Trace Buffers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Neetu Jindal, Shubhani Gupta, Divya Praneetha Ravipati, Preeti Ranjan Panda, Smruti R. Sarangi
2020 J jnl
REAL: REquest Arbitration in Last Level Caches.
ACM Trans. Embed. Comput. Syst.
Sakshi Tiwari, Shreshth Tuli, Isaar Ahmad, Ayushi Agarwal, Preeti Ranjan Panda, Sreenivas Subramoney
2019 J jnl
Alleria: An Advanced Memory Access Profiling Framework.
ACM Trans. Embed. Comput. Syst.
Hadi Brais, Preeti Ranjan Panda
2019 A* conf
DHOOM: Reusing Design-for-Debug Hardware for Online Monitoring.
DAC
Neetu Jindal, Sandeep Chandran, Preeti Ranjan Panda, Sanjiva Prasad, Abhay Mitra, Kunal Singhal, Shubham Gupta, Shikhar Tuli
2019 A conf
FastCool: Leakage Aware Dynamic Thermal Management of 3D Memories.
DATE
Lokesh Siddhu, Preeti Ranjan Panda
2019 Misc conf
Investigation of Unified Emerging-NVM SoC Architecture for IoT-WSN Applications.
VLSID
Vivek Kamalkant Parmar, Swatilekha Majumdar, Preeti Ranjan Panda, Manan Suri
2019 J jnl
PredictNcool: Leakage Aware Thermal Management for 3D Memories Using a Lightweight Temperature Predictor.
ACM Trans. Embed. Comput. Syst.
Lokesh Siddhu, Preeti Ranjan Panda
2019 — conf
Techniques for Debug of Low Power SoCs.
MTV
Sankaran M. Menon, Ashish Gupta, Chinna Prudvi, Rolf Kühnis, Sukhbinder Singh Takhar, Spencer K. Millican, Eric Rentschler, Pandy Kalimuthu, Preeti Ranjan Panda, Priyadarsan Patra
2018 Misc conf
Exploration of Loop Unroll Factors in High Level Synthesis.
VLSID
Preeti Ranjan Panda, Namita Sharma, Srikanth Kurra, Khushboo Anil Bhartia, Neeraj Kumar Singh
2018 J jnl
Reusing Trace Buffers as Victim Caches.
IEEE Trans. Very Large Scale Integr. Syst.
Neetu Jindal, Preeti Ranjan Panda, Smruti R. Sarangi
2017 A conf
A coordinated multi-agent reinforcement learning approach to multi-level cache co-partitioning.
DATE
Rahul Jain, Preeti Ranjan Panda, Sreenivas Subramoney
2017 J jnl
Cooperative Multi-Agent Reinforcement Learning-Based Co-optimization of Cores, Caches, and On-chip Network.
ACM Trans. Archit. Code Optim.
Rahul Jain, Preeti Ranjan Panda, Sreenivas Subramoney
2017 J jnl
Managing Trace Summaries to Minimize Stalls During Postsilicon Validation.
IEEE Trans. Very Large Scale Integr. Syst.
Sandeep Chandran, Preeti Ranjan Panda, Smruti R. Sarangi, Ayan Bhattacharyya, Deepak Chauhan, Sharad Kumar
2017 — ch.
Memory Architectures.
Handbook of Hardware/Software Codesign
Preeti Ranjan Panda
2017 A conf
Reusing trace buffers to enhance cache performance.
DATE
Neetu Jindal, Preeti Ranjan Panda, Smruti R. Sarangi
2016 Misc conf
A Generic Implementation of Barriers Using Optical Interconnects.
VLSID
Sandeep Chandran, Eldhose Peter, Preeti Ranjan Panda, Smruti R. Sarangi
2016 J jnl
Area-Aware Cache Update Trackers for Postsilicon Validation.
IEEE Trans. Very Large Scale Integr. Syst.
Sandeep Chandran, Smruti R. Sarangi, Preeti Ranjan Panda
2016 J jnl
Data Flow Transformation for Energy-Efficient Implementation of Givens Rotation-Based QRD.
ACM Trans. Embed. Comput. Syst.
Namita Sharma, Preeti Ranjan Panda, Francky Catthoor, Min Li, Prashant Agrawal
2016 — conf
Extending trace history through tapered summaries in post-silicon validation.
ASP-DAC
Sandeep Chandran, Preeti Ranjan Panda, Deepak Chauhan, Sharad Kumar, Smruti R. Sarangi
2016 J jnl
Integrated Exploration Methodology for Data Interleaving and Data-to-Memory Mapping on SIMD Architectures.
ACM Trans. Embed. Comput. Syst.
Iason Filippopoulos, Namita Sharma, Francky Catthoor, Per Gunnar Kjeldsberg, Preeti Ranjan Panda
2016 A conf
Machine Learned Machines: Adaptive co-optimization of caches, cores, and On-chip Network.
DATE
Rahul Jain, Preeti Ranjan Panda, Sreenivas Subramoney
2016 J jnl
Partitioning and Data Mapping in Reconfigurable Cache and Scratchpad Memory-Based Architectures.
ACM Trans. Design Autom. Electr. Syst.
Prasenjit Chakraborty, Preeti Ranjan Panda, Sandeep Sen
2015 J jnl
Array Interleaving - An Energy-Efficient Data Layout Transformation.
ACM Trans. Design Autom. Electr. Syst.
Namita Sharma, Preeti Ranjan Panda, Francky Catthoor, Praveen Raghavan, Tom Vander Aa
2015 Misc conf
Energy efficient FFT implementation through stage skipping and merging.
CODES+ISSS
Namita Sharma, Preeti Ranjan Panda, Francky Catthoor
2015 J jnl
Fundamental Results for a Generic Implementation of Barriers using Optical Interconnects.
CoRR
Sandeep Chandran, Eldhose Peter, Preeti Ranjan Panda, Smruti R. Sarangi
2015 Misc conf
Power Optimization Techniques for DDR3 SDRAM.
VLSID
Preeti Ranjan Panda, Vishal Patel, Praxal Shah, Namita Sharma, Vaidyanathan Srinivasan, Dipankar Sarma
2014 — conf
Array scalarization in high level synthesis.
ASP-DAC
Preeti Ranjan Panda, Namita Sharma, Arun Kumar Pilania, Gummidipudi Krishnaiah, Sreenivas Subramoney, Ashok Jagannathan
2014 A conf
Energy efficient data flow transformation for Givens Rotation based QR Decomposition.
DATE
Namita Sharma, Preeti Ranjan Panda, Min Li, Prashant Agrawal, Francky Catthoor
2014 A conf
Energy optimization in Android applications through wakelock placement.
DATE
Faisal Alam, Preeti Ranjan Panda, Nikhil Tripathi, Namita Sharma, Sanjiv Narayan
2014 — conf
High level energy modeling of controller logic in data caches.
ACM Great Lakes Symposium on VLSI
Preeti Ranjan Panda, Sourav Roy, Srikanth Chandrasekaran, Namita Sharma, Jasleen Kaur, Sarath Kumar Kandalam, Nagaraj N.
2014 J jnl
Shared-port register file architecture for low-energy VLIW processors.
ACM Trans. Archit. Code Optim.
Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda
2013 Misc conf
Data memory optimization in LTE downlink.
ICASSP
Namita Sharma, Tom Vander Aa, Prashant Agrawal, Praveen Raghavan, Preeti Ranjan Panda, Francky Catthoor
2013 Misc conf
Message from the program co-chairs.
CODES+ISSS
Radu Marculescu, Preeti Ranjan Panda
2013 Misc conf
Power Supply Efficiency Aware Server Allocation in Data Centers.
VLSI Design
Preeti Ranjan Panda, Manoj Jain, Anubha Verma, Dipankar Sarma, Vaidyanathan Srinivasan
2013 Misc conf
SPM-Sieve: A framework for assisting data partitioning in scratch pad memory based systems.
CASES
Prasenjit Chakraborty, Preeti Ranjan Panda
2013 A conf
Space sensitive cache dumping for post-silicon validation.
DATE
Sandeep Chandran, Smruti R. Sarangi, Preeti Ranjan Panda
2012 — conf
Efficient on-line algorithm for maintaining k-cover of sparse bit-strings.
FSTTCS
Amit Kumar, Preeti Ranjan Panda, Smruti R. Sarangi
2012 J jnl
Exploiting UML based validation for compliance checking of TLM 2 based models.
Des. Autom. Embed. Syst.
Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda
2012 Misc conf
Integrating software caches with scratch pad memory.
CASES
Prasenjit Chakraborty, Preeti Ranjan Panda
2011 B conf
A SysML Profile for Development and Early Validation of TLM 2.0 Models.
ECMFA
Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda
2011 C conf
A UML based framework for efficient validation of TLM 2 models.
FDL
Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda
2011 J jnl
Compressing Cache State for Postsilicon Processor Debug.
IEEE Trans. Computers
Preeti Ranjan Panda, M. Balakrishnan, Anant Vishnoi
2011 Misc conf
Exploiting temporal decoupling to accelerate trace-driven NoC emulation.
CODES+ISSS
Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, Anshul Kumar
2010 C conf
Enhancing post-silicon processor debug with Incremental Cache state Dumping.
VLSI-SoC
Preeti Ranjan Panda, Anant Vishnoi, M. Balakrishnan
2010 Misc conf
FastFwd: an efficient hardware acceleration technique for trace-driven network-on-chip simulation.
CODES+ISSS
Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, Anshul Kumar
2010 Misc conf
Front-End Design Flows for Systems on Chip: An Embedded Tutorial.
VLSI Design
Anshul Kumar, Preeti Ranjan Panda
2010 J jnl
Guest Editorial: Special Issue on VLSI Design and Embedded Systems.
Int. J. Parallel Program.
Preeti Ranjan Panda, Rajendran Panda
2010 Misc conf
Rank based dynamic voltage and frequency scaling fortiled graphics processors.
CODES+ISSS
B. V. N. Silpa, Gummidipudi Krishnaiah, Preeti Ranjan Panda
2009 A conf
A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors.
DATE
Aryabartta Sahu, M. Balakrishnan, Preeti Ranjan Panda
2009 — conf
Adaptive Partitioning of Vertex Shader for Low Power High Performance Geometry Engine.
ISVC (1)
B. V. N. Silpa, Kumar S. S. Vemuri, Preeti Ranjan Panda
2009 A conf
Cache aware compression for processor debug support.
DATE
Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan
2009 A* conf
Online cache state dumping for processor debug.
DAC
Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan
2008 J jnl
Guest Editor Introduction: Special Issue on Multiprocessor-based Embedded Systems.
Int. J. Parallel Program.
Preeti Ranjan Panda
2008 — conf
REWIRED - Register Write Inhibition by Resource Dedication.
ASP-DAC
Pushkar Tripathi, Rohan Jain, Srikanth Kurra, Preeti Ranjan Panda
2008 A conf
Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors.
ICCAD
B. V. N. Silpa, Anjul Patney, Tushar Krishna, Preeti Ranjan Panda, G. S. Visweswaran
2007 C conf
An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform.
ISCAS
Rahul Jain, Preeti Ranjan Panda
2007 Misc conf
Customization of Register File Banking Architecture for Low Power.
VLSI Design
Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda
2007 J jnl
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.
Int. J. Parallel Program.
Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar
2007 Misc conf
Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform.
VLSI Design
Rahul Jain, Preeti Ranjan Panda
2007 Misc conf
Power Reduction in VLIW Processor with Compiler Driven Bypass Network.
VLSI Design
Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda
2007 A conf
The impact of loop unrolling on controller delay in high level synthesis.
DATE
Srikanth Kurra, Neeraj Kumar Singh, Preeti Ranjan Panda
2006 — conf
Abridged addressing: a low power memory addressing strategy.
ASP-DAC
Preeti Ranjan Panda
2006 A* conf
Rapid estimation of control delay from high-level specifications.
DAC
Gagan Raj Gupta, Madhur Gupta, Preeti Ranjan Panda
2005 A conf
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.
DATE
Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar
2005 Misc conf
Extracting Exact Finite State Machines from Behavioral SystemC Descriptions.
VLSI Design
Vikram Singh Saun, Preeti Ranjan Panda
2003 J jnl
Memory allocation and mapping in high-level synthesis - an integrated approach.
IEEE Trans. Very Large Scale Integr. Syst.
Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda
2003 Misc conf
Specification and Design of Multi-Million Gate SOCs.
VLSI Design
Ramesh Chandra, Preeti Ranjan Panda, Jörg Henkel, Sri Parameswaran, Loganath Ramachandran
2002 A conf
An energy-conscious algorithm for memory port allocation.
ICCAD
Preeti Ranjan Panda, Lakshmikantam Chitturi
2002 A* conf
An integrated algorithm for memory allocation and assignment in high-level synthesis.
DAC
Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda
2002 Misc conf
Memory Architectures for Embedded Systems-On-Chip.
HiPC
Preeti Ranjan Panda, Nikil D. Dutt
2001 — conf
Cache-efficient memory layout of aggregate data structures.
ISSS
Preeti Ranjan Panda, Luc Séméria, Giovanni De Micheli
2001 J jnl
Data Memory Organization and Optimizations in Application-Specific Systems.
IEEE Des. Test Comput.
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau, Francky Catthoor, Arnout Vandecappelle, Erik Brockmeyer, Chidamber Kulkarni, Eddy de Greef
2001 J jnl
Data and memory optimization techniques for embedded systems.
ACM Trans. Design Autom. Electr. Syst.
Preeti Ranjan Panda, Francky Catthoor, Nikil D. Dutt, Koen Danckaert, Erik Brockmeyer, Chidamber Kulkarni, Arnout Vandecappelle, Per Gunnar Kjeldsberg
2001 Misc conf
Embedded Memories in System Design: Technology, Application, Design and Tools.
VLSI Design
Doris Keitel-Schulz, Norbert Wehn, Francky Catthoor, Preeti Ranjan Panda
2001 — conf
New Design Paradigms: What Needs to be Standardized?.
ISSS
Wolfgang Rosenstiel, Brian Bailey, Masahiro Fujita, Guang R. Gao, Rajesh K. Gupta, Preeti Ranjan Panda
2001 — conf
SystemC: A Modeling Platform Supporting Multiple Design Abstractions.
ISSS
Preeti Ranjan Panda
2000 J jnl
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems.
ACM Trans. Design Autom. Electr. Syst.
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
1999 J jnl
Augmenting Loop Tiling with Data Alignment for Improved Cache Performance.
IEEE Trans. Computers
Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau
1999 J jnl
Local memory exploration and optimization in embedded systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
1999 J jnl
Low-power memory mapping through reducing address bus activity.
IEEE Trans. Very Large Scale Integr. Syst.
Preeti Ranjan Panda, Nikil D. Dutt
1999 A conf
Memory bank customization and assignment in behavioral synthesis.
ICCAD
Preeti Ranjan Panda
1998 A conf
Data Cache Sizing for Embedded Processor Applications.
DATE
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
1998 J jnl
Incorporating DRAM access modes into high-level synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
1997 C conf
A Data Alignment Technique for Improving Cache Performance.
ICCD
Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau
1997 — conf
Architectural Exploration and Optimization of Local Memory in Embedded Systems.
ISSS
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
1997 Misc conf
Behavioral Array Mapping into Multiport Memories Targeting Low Power.
VLSI Design
Preeti Ranjan Panda, Nikil D. Dutt
1997 — conf
Efficient utilization of scratch-pad memory in embedded processor applications.
ED&TC
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
1997 A conf
Exploiting off-chip memory access modes in high-level synthesis.
ICCAD
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
1997 — conf
Improving cache Performance Through Tiling and Data Alignment.
IRREGULAR
Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau
1997 J jnl
Memory data organization for improved cache performance in embedded processor applications.
ACM Trans. Design Autom. Electr. Syst.
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
1996 A conf
Low-power mapping of behavioral arrays to multiple memories.
ISLPED
Preeti Ranjan Panda, Nikil D. Dutt
1996 — conf
Memory Organization for Improved Data Cache Performance in Embedded Processors.
ISSS
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
1996 — conf
Reducing Address Bus Transitions for Low Power Memory Mapping.
ED&TC
Preeti Ranjan Panda, Nikil D. Dutt
1995 — conf
1995 high level synthesis design repository.
ISSS
Preeti Ranjan Panda, Nikil D. Dutt
1993 J jnl
Estimating the Complexity of Synthesized Designs from FSM Specifications.
IEEE Des. Test Comput.
Biswadip Mitra, Preeti Ranjan Panda, Parimal Pal Chaudhuri
1992 Misc conf
Estimating the Complexity of Synthesized Designs from FSM Specifications.
VLSI Design
Biswadip Mitra, Preeti Ranjan Panda, Parimal Pal Chaudhuri
1991 A conf
A Flexible Scheme for State Assignment Based on Characteristics of the FSM.
ICCAD
Biswadip Mitra, Preeti Ranjan Panda, Parimal Pal Chaudhuri