Prashant Saxena

46 papers A* 4A 2C 1Misc 1Journal 18Unranked 15

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Surface stability of a layered magnetoelastic half-space. CoRR Davood Shahsavari, Luis Dorfmann, Prashant Saxena
2024	J	`jnl`	Plane stress finite element modelling of arbitrary compressible hyperelastic materials. CoRR Masoud Ahmadi, Andrew McBride, Paul Steinmann, Prashant Saxena
2022	J	`jnl`	An Accurate, Error-Tolerant, and Energy-Efficient Neural Network Inference Engine Based on SONOS Analog Memory. IEEE Trans. Circuits Syst. I Regul. Pap. T. Patrick Xiao, Ben Feinberg, Christopher H. Bennett, Vineet Agrawal, Prashant Saxena, Venkatraman Prabhakar, Krishnaswamy Ramkumar, Harsha Medu, Vijay Raghavan, Ramesh Chettuvetty, Sapan Agarwal, Matthew J. Marinella
2022	J	`jnl`	Computational bifurcation analysis of hyperelastic thin shells. CoRR Zhaowei Liu, Andrew McBride, Abhishek Ghosh, Luca Heltai, Weicheng Huang, Tiantang Yu, Paul Steinmann, Prashant Saxena
2021	—	`conf`	Image GPT with Super Resolution. FICTA (1) Bhumika Shah, Ankita Sinha, Prashant Saxena
2021	J	`jnl`	On the Accuracy of Analog Neural Network Inference Accelerators. CoRR T. Patrick Xiao, Ben Feinberg, Christopher H. Bennett, Venkatraman Prabhakar, Prashant Saxena, Vineet Agrawal, Sapan Agarwal, Matthew J. Marinella
2021	J	`jnl`	Vibration Analysis of Piezoelectric Kirchhoff-Love Shells based on Catmull-Clark Subdivision Surfaces. CoRR Zhaowei Liu, Andrew McBride, Prashant Saxena, Luca Heltai, Yilin Qu, Paul Steinmann
2019	J	`jnl`	Aspects of Isogeometric Analysis with Catmull-Clark Subdivision Surfaces. CoRR Zhaowei Liu, Andrew McBride, Prashant Saxena, Paul Steinmann
2017	—	`conf`	Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning. ISPD Wei-Ting Jonas Chan, Pei-Hsin Ho, Andrew B. Kahng, Prashant Saxena
2014	A	`conf`	Aerie: flexible file-system interfaces to storage-class memory. EuroSys Haris Volos, Sanketh Nalli, Sankaralingam Panneerselvam, Venkatanathan Varadarajan, Prashant Saxena, Michael M. Swift
2012	—	`conf`	On pioneering nanometer-era routing problems. ISPD Tong Gao, Prashant Saxena
2011	J	`jnl`	Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Prashant Saxena, Yao-Wen Chang
2011	—	`conf`	Multi-mode redundancy removal. ISQED Stephen M. Plaza, Prashant Saxena, Thomas R. Shiple, Pei-Hsin Ho
2010	J	`jnl`	Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gi-Joon Nam, Prashant Saxena
2010	—	`ed.`	Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010 ISPD Prashant Saxena, Yao-Wen Chang
2009	—	`conf`	On improving optimization effectiveness in interconnect-driven physical synthesis. ISPD Prashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, J.-C. Lin, Mahesh A. Iyer
2009	—	`ed.`	Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009 ISPD Gi-Joon Nam, Prashant Saxena
2008	—	`ch.`	Estimation of Routing Congestion. Handbook of Algorithms for Physical Design Automation Rupesh S. Shelar, Prashant Saxena
2007	—	`book`	Routing Congestion in VLSI Circuits - Estimation and Optimization. Prashant Saxena, Rupesh S. Shelar, Sachin S. Sapatnekar
2006	J	`jnl`	On controlling perturbation due to repeaters during quadratic placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Prashant Saxena
2006	J	`jnl`	Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rupesh S. Shelar, Prashant Saxena, Sachin S. Sapatnekar
2006	—	`conf`	The scaling of interconnect buffer needs. SLIP Prashant Saxena
2005	—	`conf`	A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. ISCAS (6) Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani
2005	—	`conf`	A perturbation-aware noise convergence methodology for high frequency microprocessors. ASP-DAC Prashant Saxena, Kumar N. Lalgudi, Hans J. Greub, Janet Meiling Wang Roveda
2005	J	`jnl`	A predictive distributed congestion metric with application to technology mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang
2005	—	`conf`	An efficient technology mapping algorithm targeting routing congestion under delay constraints. ISPD Rupesh S. Shelar, Prashant Saxena, Xinning Wang, Sachin S. Sapatnekar
2005	A*	`conf`	Net weighting to reduce repeater counts during placement. DAC Brent Goplen, Prashant Saxena, Sachin S. Sapatnekar
2004	—	`conf`	A predictive distributed congestion metric and its application to technology mapping. ISPD Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang
2004	A*	`conf`	Modeling repeaters explicitly within analytical placement. DAC Prashant Saxena, Bill Halpin
2004	—	`conf`	Realizable parasitic reduction for distributed interconnects using matrix pencil technique. ASP-DAC Janet Meiling Wang, Prashant Saxena, Omar Hafiz, Xing Wang
2004	J	`jnl`	Repeater scaling and its impact on CAD. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick
2004	—	`conf`	The great interconnect buffering debate: are you a chicken or an ostrich? ISPD Desmond Kirkpatrick, Peter J. Osler, Louis Scheffer, Prashant Saxena, Dennis Sylvester
2003	J	`jnl`	Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. IEEE Trans. Very Large Scale Integr. Syst. Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang
2003	J	`jnl`	On integrating power and signal routing for shield count minimization in congested regions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Prashant Saxena, Satyanarayan Gupta
2003	—	`conf`	The scaling challenge: can correct-by-construction design help? ISPD Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick
2002	C	`conf`	A System-Level Solution to Domino Synthesis with 2 GHz Application. ICCD B. Chappell, Xinning Wang, Priyadarsan Patra, Prashant Saxena, J. Vendrell, Satyanarayan Gupta, S. Varadarajan, W. Gomes, S. Hussain, H. Krishnamurthy, M. Venkateshmurthy, S. Jain
2002	—	`conf`	Shield count minimization in congested regions. ISPD Prashant Saxena, Satyanarayan Gupta
2001	A*	`conf`	Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. DAC Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang
2001	J	`jnl`	Optimization of the maximum delay of global interconnects duringlayer assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Prashant Saxena, C. L. Liu
2000	J	`jnl`	A postprocessing algorithm for crosstalk-driven wire perturbation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Prashant Saxena, C. L. Liu
1999	A*	`conf`	Crosstalk Minimization Using Wire Perturbations. DAC Prashant Saxena, C. L. Liu
1999	Misc	`conf`	The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. VLSI Design Prashant Saxena, Peichen Pan, C. L. Liu
1998	A	`conf`	A performance-driven layer assignment algorithm for multiple interconnect trees. ICCAD Prashant Saxena, C. L. Liu
1998	—	`—`	The Retiming and Routing of VLSI Circuits Prashant Saxena
1996	—	`conf`	A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. Euro-Par, Vol. I Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu
1994	J	`jnl`	Efficient Management of Dynamic Tables. Inf. Process. Lett. Aviezri S. Fraenkel, Edward M. Reingold, Prashant Saxena