Prashant Dubey

12 papers C 3Misc 3Journal 2Unranked 4
YearRankTypeTitle / Venue / Authors
2025 J jnl
Interconnect/Memory Co-Design and Co-Optimization Using Differential Transmission Lines.
IEEE Trans. Very Large Scale Integr. Syst.
Zhenlin Pei, Hsiao-Hsuan Liu, Mahta Mayahinia, Mehdi B. Tahoori, Francky Catthoor, Zsolt Tokei, Prashant Dubey, Chenyun Pan
2017 C conf
A 0.42V high bandwidth synthesizable parallel access smart memory fabric for computer vision.
ISCAS
Prashant Dubey, Kritika Aditya, Ankur Srivastava, Amit Khanuja, Jamil Kawa, Thu Nguyen
2014 Misc conf
A 500 mV to 1.0 V 128 Kb SRAM in Sub 20 nm Bulk-FinFET Using Auto-adjustable Write Assist.
VLSID
Prashant Dubey, Gaurav Ahuja, Vaibhav Verma, Sanjay Kumar Yadav, Amit Khanuja
2013 Misc conf
38dB Tuning Range Coupled VCO Based Divider Architecture with 68uW Power @2.0 GHz in 65nm CMOS.
VLSI Design
Prashant Dubey, Rashmi Agarwal
2013 Misc conf
PODIA: Power Optimization through Differential Imbalanced Amplifier.
VLSI Design
Prashant Dubey, Atul Kumar Kashyap, Navneet Gupta, Kaushik Saha
2010 J jnl
Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test Time.
J. Electron. Test.
Prashant Dubey, Akhil Garg, Shashank Mahajan
2008 — conf
On Chip Jitter Measurement through a High Accuracy TDC.
ISQED
Akhil Garg, Prashant Dubey
2007 C conf
Built in Defect Prognosis for Embedded Memories.
DDECS
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani
2007 C conf
GALS Based Shared Test Architecture for Embedded Memories.
ISCAS
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani
2007 — conf
Low Area Adaptive Fail-Data Compression Methodology for Defect Classification and Production Phase Prognosis.
ISVLSI
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani
2006 — conf
Fuse Area Reduction Based on Quantitative Yield Analysis and Effective Chip Cost.
SoCC
Akhil Garg, Prashant Dubey
2006 — conf
Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost.
DFT
Akhil Garg, Prashant Dubey