Pranose J. Edavoor

22 papers C 2Misc 2Journal 11Unranked 7
YearRankTypeTitle / Venue / Authors
2026 Misc conf
Design and Analysis of Fused SIM(S)D Functional Units for RISC-V P-and-B Extensions Instructions.
VLSID
Nancy Gupta, David Selvakumar, Gopal Raut, Pranose J. Edavoor
2024 J jnl
A Novel Design Approach and VLSI Architecture of Rationalized Bi-Orthogonal Wavelet Filter Banks.
IEEE Trans. Very Large Scale Integr. Syst.
Aswini K. Samantaray, Pranose J. Edavoor, Amol D. Rahulkar
2024 — conf
A SIMD Dynamic Fixed Point Processing Engine for DNN Accelerators.
ISQED
Gopal Raut, Pranose J. Edavoor, David Selvakumar, Ritambhara Thakur
2023 Misc conf
Design and Analysis of Posit Quire Processing Engine for Neural Network Applications.
VLSID
Pranose J. Edavoor, Aneesh Raveendran, David Selvakumar, Vivian Desalphine, Shankar G. Dharani, Gopal Raut
2023 J jnl
Power-Efficient VLSI Architecture of a New Class of Dyadic Gabor Wavelets for Medical Image Retrieval.
IEEE Trans. Very Large Scale Integr. Syst.
Aswini K. Samantaray, Pranose J. Edavoor, Amol D. Rahulkar
2022 J jnl
A New Approach to the Design and Implementation of a Family of Multiplier Free Orthogonal Wavelet Filter Banks.
IEEE Trans. Circuits Syst. Video Technol.
Aswini K. Samantaray, Pranose J. Edavoor, Amol D. Rahulkar
2022 J jnl
A Novel Design of Symmetric Daub-4 Wavelet Filter Bank for Image Analysis.
IEEE Trans. Circuits Syst. II Express Briefs
Aswini K. Samantaray, Pranose J. Edavoor, Amol D. Rahulkar
2022 C conf
On The Design Of Rationalised Bi-orthogonal Wavelet Using Reversible Logic.
ISCAS
Sithara Raveendran, Pranose J. Edavoor, Y. B. Nithin Kumar, M. H. Vasantha
2021 J jnl
A Novel Design of Dyadic db3 Orthogonal Wavelet Filter Bank for Feature Extraction.
Circuits Syst. Signal Process.
Aswini K. Samantaray, Amol D. Rahulkar, Pranose J. Edavoor
2021 J jnl
Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic.
IEEE Access
Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Yernad Balachandra, M. H. Vasantha
2021 J jnl
Novel 4: 2 Approximate Compressor Designs for Multimedia and Neural Network Applications.
J. Circuits Syst. Comput.
Pranose J. Edavoor, Sithara Raveendran, Amol D. Rahulkar
2020 J jnl
An Approximate Low-Power Lifting Scheme Using Reversible Logic.
IEEE Access
Sithara Raveendran, Pranose J. Edavoor, Nithin Y. B. Kumar, M. H. Vasantha
2020 J jnl
Approximate Multiplier Design Using Novel Dual-Stage 4: 2 Compressors.
IEEE Access
Pranose J. Edavoor, Sithara Raveendran, Amol D. Rahulkar
2020 J jnl
Design and implementation of image kernels using reversible logic gates.
IET Image Process.
Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra
2020 — conf
Reversible Logic Implementation of Image Denoising for Grayscale Images.
MWSCAS
Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Y. B., M. H. Vasantha
2019 J jnl
Design and implementation of a novel low complexity symmetric orthogonal wavelet filter-bank.
IET Image Process.
Pranose J. Edavoor, Amol D. Rahulkar
2018 C conf
Design and Implementation of Reversible Logic based RGB to Gray scale Color Space Converter.
TENCON
Sithara Raveendran, Pranose J. Edavoor, Nithin Y. B. Kumar, M. H. Vasantha
2017 — conf
Design and implementation of PID controller based on orthogonal wavelet filter-banks in FPGA.
ISED
Priyanandini Das, Pranose J. Edavoor, Sithara Raveendran, Sunil Rathore, Amol D. Rahulkar
2017 — conf
Implementation of adaptive image compression algorithm using varying bit-length daubechies wavelet coefficient with three-level encryption on Zynq 7000.
ISED
Pranose J. Edavoor, Sithara Raveendran, Amol D. Rahulkar
2016 — conf
FPGA realisation of PSNR and BPP driven Adaptive Compression and Encryption Algorithm for RGB Images.
ICCCNT
Pranose J. Edavoor, Sithara Raveendran, Arjun T. V., Sumesh K. P., Kumar Y. B. Nithin, M. H. Vasantha
2015 — conf
An efficient approach for design and testing of FPGA programming using Lab VIEW.
ICACCI
B. Naresh Kumar Reddy, N. Suresh, Janjhyam Venkata Naga Ramesh, T. Pavithra, Y. Krupa Bahulya, Pranose J. Edavoor, S. Janaki Ram
2015 — conf
Poster: An Efficient Low Power & High Performance in MPSOC.
WCI
K. Jayasree, B. Naresh Kumar Reddy, B. Srinuvasu Kumar, Janjhyam Venkata Naga Ramesh, Pranose J. Edavoor, Mohd Kashif Zia Ansari