Pranav Ashar - RankMe

70 papers A* 15A 13B 4C 3Misc 7Journal 19Unranked 9

Year	Rank	Type	Title / Venue / Authors
2019	—	`conf`	Closing the Verification Gap with Static Sign-off. ISQED Pranav Ashar, Vinod Viswanath
2017	—	`conf`	Failures and verification solutions related to untimed paths in SOCs. ISQED Pranav Ashar, Vikas Sachdeva, Vinod Viswanath
2016	B	`conf`	A paradigm shift in verification methodology. FMCAD Pranav Ashar
2013	B	`conf`	Static verification based signoff - A key enabler for managing verification complexity in the modern soc. FMCAD Pranav Ashar
2010	—	`conf`	Clock domain verification challenges and scalable solutions. HLDVT Pranav Ashar
2008	J	`jnl`	Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Aleksandr Zaks, Zijiang Yang, Ilya Shlyakhter, Franjo Ivancic, Srihari Cadambi, Malay K. Ganai, Aarti Gupta, Pranav Ashar
2008	J	`jnl`	Efficient SAT-based bounded model checking for software verification. Theor. Comput. Sci. Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Pranav Ashar
2007	J	`jnl`	Verification of Embedded Memory Systems using Efficient Memory Modeling CoRR Malay K. Ganai, Aarti Gupta, Pranav Ashar
2006	J	`jnl`	Efficient distributed SAT and SAT-based distributed Bounded Model Checking. Int. J. Softw. Tools Technol. Transf. Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar
2006	—	`conf`	Panel: Assertion-Based Verification -What's the Big Deal? HLDVT Sandeep K. Shukla, Alan J. Hu, Jacob Abrahams, Pranav Ashar, Harry Foster, Avner Landver, Carl Pixley
2005	A*	`conf`	Beyond safety: customized SAT-based model checking. DAC Malay K. Ganai, Aarti Gupta, Pranav Ashar
2005	A*	`conf`	F-Soft: Software Verification Platform. CAV Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Ilya Shlyakhter, Pranav Ashar
2005	Misc	`conf`	Lazy Constraints and SAT Heuristics for Proof-Based Abstraction. VLSI Design Aarti Gupta, Malay K. Ganai, Pranav Ashar
2005	A	`conf`	Verification of Embedded Memory Systems using Efficient Memory Modeling. DATE Malay K. Ganai, Aarti Gupta, Pranav Ashar
2004	A*	`conf`	Efficient Modeling of Embedded Memories in Bounded Model Checking. CAV Malay K. Ganai, Aarti Gupta, Pranav Ashar
2004	—	`conf`	Efficient SAT-based Bounded Model Checking for Software Verification. ISoLA (Preliminary proceedings) Pranav Ashar, Malay K. Ganai, Aarti Gupta, Franjo Ivancic, Zijiang Yang
2004	A	`conf`	Efficient SAT-based unbounded symbolic model checking using circuit cofactoring. ICCAD Malay K. Ganai, Aarti Gupta, Pranav Ashar
2003	A*	`conf`	Abstraction and BDDs Complement SAT-Based BMC in DiVer. CAV Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar
2003	—	`conf`	Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking. CHARME Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar
2003	A	`conf`	Iterative Abstraction using SAT-based BMC with Proof Analysis. ICCAD Aarti Gupta, Malay K. Ganai, Zijiang Yang, Pranav Ashar
2003	A*	`conf`	Learning from BDDs in SAT-based bounded model checking. DAC Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar
2002	A*	`conf`	A fast, inexpensive and scalable hardware acceleration technique for functional simulation. DAC Srihari Cadambi, Chandra Mulpuri, Pranav Ashar
2002	A*	`conf`	Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver. DAC Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao Zhang, Sharad Malik
2002	J	`jnl`	Functional vector generation for sequential HDL models under an observability-based code coverage metric. IEEE Trans. Very Large Scale Integr. Syst. Farzan Fallah, Pranav Ashar, Srinivas Devadas
2002	—	`conf`	Property-Specific Testbench Generation for Guided Simulation. ASP-DAC/VLSI Design Aarti Gupta, Albert E. Casavant, Pranav Ashar, Sean Liu, Akira Mukaiyama, Kazutoshi Wakabayashi
2001	A*	`conf`	Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation. DAC Aarti Gupta, Anubhav Gupta, Zijiang Yang, Pranav Ashar
2001	A	`conf`	Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs. ICCAD Aarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zhang, Sharad Malik
2001	A	`conf`	Property-specific witness graph generation for guided simulation. DATE Albert E. Casavant, Aarti Gupta, S. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi, Pranav Ashar
2001	J	`jnl`	Using complete-1-distinguishability for FSM equivalence checking. ACM Trans. Design Autom. Electr. Syst. Pranav Ashar, Aarti Gupta, Sharad Malik
2000	J	`jnl`	An Edge-endpoint-based Configurable Hardware Architecture for VLSI Layout Design Rule Checking. VLSI Design Zhen Luo, Margaret Martonosi, Pranav Ashar
2000	Misc	`conf`	Fast Error Diagnosis for Combinational Verification. VLSI Design Aarti Gupta, Pranav Ashar
2000	B	`conf`	SAT-Based Image Computation with Application in Reachability Analysis. FMCAD Aarti Gupta, Zijiang Yang, Pranav Ashar, Anubhav Gupta
2000	Misc	`conf`	Verification of a Combinational Loop Based Arbitration Scheme in a System-On-Chip Integration Architecture. VLSI Design Yang Xia, Pranav Ashar
1999	Misc	`conf`	An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking. FCCM Zhen Luo, Margaret Martonosi, Pranav Ashar
1999	—	`conf`	Exploiting Retiming in a Guided Simulation Based Validation Methodology. CHARME Aarti Gupta, Pranav Ashar, Sharad Malik
1999	A*	`conf`	Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage. DAC Farzan Fallah, Pranav Ashar, Srinivas Devadas
1999	J	`jnl`	Using configurable computing to accelerate Boolean satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik
1999	C	`conf`	Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation. ICCD Pranav Ashar, Anand Raghunathan, Aarti Gupta, Subhrajit Bhattacharya
1998	Misc	`conf`	Accelerating Boolean Satisfiability with Configurable Hardware. FCCM Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik
1998	J	`jnl`	Guarded evaluation: pushing power management to logic synthesis/design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vivek Tiwari, Sharad Malik, Pranav Ashar
1998	Misc	`conf`	Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking. VLSI Design Aarti Gupta, Pranav Ashar
1998	B	`conf`	Solving Boolean Satisfiability with Dynamic Hardware Configurations. FPL Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik
1998	A*	`conf`	Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability. DAC Peixin Zhong, Pranav Ashar, Sharad Malik, Margaret Martonosi
1998	A	`conf`	Verification of RTL generated from scheduled behavior in a high-level synthesis flow. ICCAD Pranav Ashar, Subhrajit Bhattacharya, Anand Raghunathan, Akira Mukaiyama
1997	A*	`conf`	Toward Formalizing a Validation Methodology Using Simulation Coverage. DAC Aarti Gupta, Sharad Malik, Pranav Ashar
1996	A*	`conf`	Scheduling Techniques to Enable Power Management. DAC José Monteiro, Srinivas Devadas, Pranav Ashar, Ashutosh Mauskar
1996	J	`jnl`	Technology mapping for low power in logic synthesis. Integr. Vivek Tiwari, Pranav Ashar, Sharad Malik
1996	A	`conf`	Using complete-1-distinguishability for FSM equivalence checking. ICCAD Pranav Ashar, Aarti Gupta, Sharad Malik
1995	J	`jnl`	Exploiting multicycle false paths in the performance optimization of sequential logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pranav Ashar, Sujit Dey, Sharad Malik
1995	A	`conf`	Fast functional simulation using branching programs. ICCAD Pranav Ashar, Sharad Malik
1995	J	`jnl`	Functional timing analysis using ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pranav Ashar, Sharad Malik
1995	—	`conf`	Guarded evaluation: pushing power management to logic synthesis/design. ISLPD Vivek Tiwari, Sharad Malik, Pranav Ashar
1995	Misc	`conf`	Test generation for cyclic combinational circuits. VLSI Design Anand Raghunathan, Pranav Ashar, Sharad Malik
1995	J	`jnl`	Test generation for cyclic combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Anand Raghunathan, Pranav Ashar, Sharad Malik
1994	A	`conf`	Efficient breadth-first manipulation of binary decision diagrams. ICCAD Pranav Ashar, Matthew Cheong
1994	A*	`conf`	Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications. DAC Pranav Ashar, Sharad Malik
1993	J	`jnl`	Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks. Formal Methods Syst. Des. Pranav Ashar, Srinivas Devadas, Kurt Keutzer
1993	J	`jnl`	Path-delay-fault testability properties of multiplexor-based networks. Integr. Pranav Ashar, Srinivas Devadas, Kurt Keutzer
1993	A*	`conf`	Technology Mapping for Lower Power. DAC Vivek Tiwari, Pranav Ashar, Sharad Malik
1992	J	`jnl`	Boolean satisfiability and equivalence checking using general Binary Decision Diagrams. Integr. Pranav Ashar, Abhijit Ghosh, Srinivas Devadas
1992	A	`conf`	Exploiting multi-cycle false paths in the performance optimization of sequential circuits. ICCAD Pranav Ashar, Sujit Dey, Sharad Malik
1991	C	`conf`	Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams. ICCD Pranav Ashar, Abhijit Ghosh, Srinivas Devadas
1991	A	`conf`	Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks. ITC Pranav Ashar, Srinivas Devadas, Kurt Keutzer
1991	J	`jnl`	Irredundant interacting sequential machines via optimal logic synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pranav Ashar, Srinivas Devadas, A. Richard Newton
1991	J	`jnl`	Optimum and heuristic algorithms for an approach to finite state machine decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pranav Ashar, Srinivas Devadas, A. Richard Newton
1990	A*	`conf`	A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines. DAC Pranav Ashar, Srinivas Devadas, A. Richard Newton
1990	A	`conf`	Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test. ICCAD Pranav Ashar, Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
1990	C	`conf`	Testability driven synthesis of interacting finite state machines. ICCD Pranav Ashar, Srinivas Devadas, A. Richard Newton
1989	A	`conf`	Optimum and heuristic algorithms for finite state machine decomposition and partitioning. ICCAD Pranav Ashar, Srinivas Devadas, A. Richard Newton
1988	J	`jnl`	Magnitude locked loop. Proc. IEEE K. Radhakrishna Rao, Pranav Ashar