Pramod Kumar Meher

190 papers B 12C 28Misc 2Journal 122Unranked 26
YearRankTypeTitle / Venue / Authors
2026 J jnl
Low complexity object-aware axial partitioning of images using efficient boundary extraction.
Signal Image Video Process.
Tapaswini Pattnaik, Pramod Kumar Meher
2025 J jnl
A Flexible DA-Based Architecture for Computation of Inner Product of Variable Vectors.
IEEE Trans. Very Large Scale Integr. Syst.
Anil Kali, Samrat L. Sabat, Pramod Kumar Meher
2025 J jnl
Efficient Design and Implementation of Scale-Free CORDIC With Mutually Exclusive Micro-Rotations.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pramod Kumar Meher, Supriya Aggarwal
2025 J jnl
FPGA-Specific Efficient Designs of Digit-Serial Multiplier for Galois Field GF(2
Circuits Syst. Signal Process.
Dibakar Pradhan, Pramod Kumar Meher, Bimal Kumar Meher
2024 C conf
A Novel DA-Based Parallel Architecture for Inner-Product of Variable Vectors.
ISCAS
Anil Kali, Samrat L. Sabat, Pramod Kumar Meher
2024 J jnl
Advancements in Deep Learning for B-Mode Ultrasound Segmentation: A Comprehensive Review.
IEEE Trans. Emerg. Top. Comput. Intell.
Mohammed Yusuf Ansari, Iffa Afsa Changaai Mangalote, Pramod Kumar Meher, Omar Aboumarzouk, Abdulla Al-Ansari, Osama Halabi, Sarada Prasad Dakua
2024 J jnl
Design of a Novel Inexact 4:2 Compressor and Its Placement in the Partial Product Array for Area, Delay, and Power-Efficient Approximate Multipliers.
Circuits Syst. Signal Process.
Srikant Kumar Beura, Bishnulatpam Pushpa Devi, Prabir Saha, Pramod Kumar Meher
2024 — conf
Efficient Implementation of Entity On-Boarding and Authentication in Zero-Trust Systems.
PKIA
Jayashree Rana, Pramod Kumar Meher, Rojalina Priyadarshini, K. Pratyush Rao
2024 J jnl
Input-Output Scheduling and Control for Efficient FPGA Realization of Digit-Serial Multiplication Over Generic Binary Extension Fields.
Circuits Syst. Signal Process.
Dibakar Pradhan, Pramod Kumar Meher, Bimal Kumar Meher
2024 J jnl
Low Complexity Design of Logistic Distance Metric Adaptive Filter for Impulsive Noise Environments.
IEEE Trans. Very Large Scale Integr. Syst.
Shouharda Ghosh, Pramod Kumar Meher, Dwaipayan Ray, Nithin V. George
2023 J jnl
An Efficient Scaling-Free Folded Hyperbolic CORDIC Design Using a Novel Low-Complexity Power-of-2 Taylor Series Approximation.
IEEE Trans. Very Large Scale Integr. Syst.
Anu Verma, Khyati Kiyawat, Bishnu Prasad Das, Pramod Kumar Meher
2023 J jnl
Dense-PSP-UNet: A neural network for fast inference liver ultrasound segmentation.
Comput. Biol. Medicine
Mohammed Yusuf Ansari, Yin Yang, Pramod Kumar Meher, Sarada Prasad Dakua
2023 J jnl
Low-Complexity Distributed Arithmetic-Based Architecture for Inner-Product of Variable Vectors.
IEEE Trans. Very Large Scale Integr. Syst.
Anil Kali, Samrat L. Sabat, Pramod Kumar Meher
2022 J jnl
Energy-Efficient High-Speed ASIC Implementation of Convolutional Neural Network Using Novel Reduced Critical-Path Design.
IEEE Access
Sun Sik Lee, Thanh Dat Nguyen, Pramod Kumar Meher, Sang Yoon Park
2022 J jnl
Enhanced Sharpening of CIC Decimation Filters, Implementation and Applications.
Circuits Syst. Signal Process.
Supriya Aggarwal, Pramod Kumar Meher
2021 J jnl
Design of Very High-Speed Pipeline FIR Filter Through Precise Critical Path Analysis.
IEEE Access
Su Min Cho, Pramod Kumar Meher, Luong Tran Nhat Trung, Hyo Jin Cho, Sang Yoon Park
2020 J jnl
An Analytical Framework and Approximation Strategy for Efficient Implementation of Distributed Arithmetic-Based Inner-Product Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap.
Dwaipayan Ray, Nithin V. George, Pramod Kumar Meher
2020 J jnl
An Efficient Parallel DA-Based Fixed-Width Design for Approximate Inner-Product Computation.
IEEE Trans. Very Large Scale Integr. Syst.
Basant Kumar Mohanty, Pramod Kumar Meher
2020 J jnl
Analysis and Design of Unified Architectures for Zero-Attraction-Based Sparse Adaptive Filters.
IEEE Trans. Very Large Scale Integr. Syst.
Dwaipayan Ray, Nithin V. George, Pramod Kumar Meher
2020 J jnl
Efficient approximate core transform and its reconfigurable architectures for HEVC.
J. Real Time Image Process.
Maher Jridi, Ayman Alfalou, Pramod Kumar Meher
2019 J jnl
50 Years of FFT Algorithms and Applications.
Circuits Syst. Signal Process.
G. Ganesh Kumar, Subhendu Kumar Sahoo, Pramod Kumar Meher
2019 C conf
Analysis and Design of Approximate Inner-Product Architectures Based on Distributed Arithmetic.
ISCAS
Dwaipayan Ray, Nithin V. George, Pramod Kumar Meher
2019 J jnl
Analysis of Systolic Penalties and Design of Efficient Digit-Level Systolic-like Multiplier for Binary Extension Fields.
Circuits Syst. Signal Process.
Bimal Kumar Meher, Pramod Kumar Meher
2019 J jnl
Area-Delay-Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data.
IEEE Trans. Circuits Syst. I Regul. Pap.
Basant K. Mohanty, Pramod Kumar Meher
2019 — conf
Low Latency Scaling-Free Pipeline CORDIC Architecture Using Augmented Taylor Series.
iSES
Sumit Satyavijay Wadkar, Bishnu Prasad Das, Pramod Kumar Meher
2019 C conf
Low-Complexity Systolic Multiplier for GF(2
ISCAS
Jiafeng Xie, Chiou-Yng Lee, Pramod Kumar Meher
2019 J jnl
Multichannel Filters for Wireless Networks: Lookup-Table-Based Efficient Implementation.
IEEE Consumer Electron. Mag.
Subhendu Kumar Sahoo, Pramod Kumar Meher, Ganesh Kumar Ganjikunta
2019 J jnl
Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis.
IEEE Trans. Very Large Scale Integr. Syst.
Jiafeng Xie, Chiou-Yng Lee, Pramod Kumar Meher, Zhi-Hong Mao
2018 J jnl
Efficient Cross-Correlation Algorithm and Architecture for Robust Synchronization in Frame-Based Communication Systems.
Circuits Syst. Signal Process.
Syed Naveen Altaf Ahmed, Pramod Kumar Meher, Achutavarrier Prasad Vinod
2018 J jnl
Efficient Shift-Add Implementation of FIR Filters Using Variable Partition Hybrid Form Structures.
IEEE Trans. Circuits Syst. I Regul. Pap.
Dwaipayan Ray, Nithin V. George, Pramod Kumar Meher
2018 J jnl
Low Register-Complexity Systolic Digit-Serial Multiplier Over GF(2
IEEE Trans. Multi Scale Comput. Syst.
Jiafeng Xie, Pramod Kumar Meher, Xiaojun Zhou, Chiou-Yng Lee
2018 J jnl
Threshold-Guided Design and Optimization for Harris Corner Detector Architecture.
IEEE Trans. Circuits Syst. Video Technol.
Bhavan A. Jasani, Siew-Kei Lam, Pramod Kumar Meher, Meiqing Wu
2017 J jnl
Efficient FPGA Implementation of Low-Complexity Systolic Karatsuba Multiplier Over GF(2
IEEE Trans. Circuits Syst. I Regul. Pap.
Jiafeng Xie, Pramod Kumar Meher, Mingui Sun, Yuecheng Li, Bo Zeng, Zhi-Hong Mao
2017 — conf
Lookup Table-Based Low-Power Implementation of Multi-channel Filters for Software Defined Radio.
iNIS
Subhendu Kumar Sahoo, Pramod Kumar Meher
2017 J jnl
Low-Complexity Digit-Serial Multiplier Over $GF(2^{m})$ Based on Efficient Toeplitz Block Toeplitz Matrix-Vector Product Decomposition.
IEEE Trans. Very Large Scale Integr. Syst.
Chiou-Yng Lee, Pramod Kumar Meher, Chia-Chen Fan, Shyan-Ming Yuan
2017 J jnl
Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for GF(2
IEEE Trans. Circuits Syst. I Regul. Pap.
Pramod Kumar Meher, Xin Lou
2017 J jnl
Lower Bound Analysis and Perturbation of Critical Path for Area-Time Efficient Multiple Constant Multiplications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xin Lou, Ya Jun Yu, Pramod Kumar Meher
2017 J jnl
Novel Structure for Area-Efficient Implementation of FIR Filters.
IEEE Trans. Circuits Syst. II Express Briefs
Xin Lou, Pramod Kumar Meher, Yajun Yu, Wenbin Ye
2017 J jnl
Scalable Approximate DCT Architectures for Efficient HEVC-Compliant Video Coding.
IEEE Trans. Circuits Syst. Video Technol.
Maher Jridi, Pramod Kumar Meher
2016 J jnl
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Basant Kumar Mohanty, Pramod Kumar Meher
2016 J jnl
A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic.
Integr.
Basant Kumar Mohanty, Pramod Kumar Meher, Subodh Kumar Singhal, M. N. S. Swamy
2016 J jnl
Analysis and Optimization of Product-Accumulation Section for Efficient Implementation of FIR Filters.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xin Lou, Ya Jun Yu, Pramod Kumar Meher
2016 J jnl
Area-Delay Efficient Digit-Serial Multiplier Based on k-Partitioning Scheme Combined With TMVP Block Recombination Approach.
IEEE Trans. Very Large Scale Integr. Syst.
Chiou-Yng Lee, Pramod Kumar Meher, Chung-Hsin Liu
2016 J jnl
Comment on "Subquadratic Space-Complexity Digit-Serial Multipliers Over GF(2
IEEE Trans. Circuits Syst. I Regul. Pap.
Chiou-Yng Lee, Pramod Kumar Meher
2016 J jnl
Concept, Design, and Implementation of Reconfigurable CORDIC.
IEEE Trans. Very Large Scale Integr. Syst.
Supriya Aggarwal, Pramod Kumar Meher, Kavita Khare
2016 J jnl
Introduction of New Associate Editors.
IEEE Trans. Circuits Syst. Video Technol.
Nikolaos V. Boulgouris, David R. Bull, Marco Cagnazzo, Andrea Cavallaro, Gene Cheung, Amit K. Roy-Chowdhury, Pedro Comesaña Alfaro, Shan Du, Sarp Ertürk, Markus Flierl, Gian Luca Foresti, Gang Hua, Zhu Li, Weisi Lin, Siwei Ma, Pramod Kumar Meher, Debargha Mukherjee, Aleksandra Pizurica, Andrea Prati, Paolo Remagnino, Arun Ross, Shin'ichi Satoh, Andreas E. Savakis, Heiko Schwarz, Ling Shao, Shervin Shirmohammadi, Giuseppe Valenzise, Meng Wang, Zhou Wang, Yonggang Wen, Dong Xu, Junsong Yuan, Yuan Yuan
2016 J jnl
LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter.
IEEE Trans. Very Large Scale Integr. Syst.
Basant K. Mohanty, Pramod Kumar Meher, Sujit Kumar Patel
2016 J jnl
On Efficient Retiming of Fixed-Point Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Pramod Kumar Meher
2016 J jnl
Seamless Pipelining of DSP Circuits.
Circuits Syst. Signal Process.
Pramod Kumar Meher
2015 J jnl
A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT.
IEEE Trans. Circuits Syst. I Regul. Pap.
Maher Jridi, Ayman Alfalou, Pramod Kumar Meher
2015 J jnl
Area-Efficient Subquadratic Space-Complexity Digit-Serial Multiplier for Type-II Optimal Normal Basis of GF(2
IEEE Trans. Circuits Syst. I Regul. Pap.
Chiou-Yng Lee, Pramod Kumar Meher
2015 C conf
Critical-path optimization for efficient hardware realization of lifting and flipping DWTs.
ISCAS
Basant K. Mohanty, Pramod Kumar Meher, Thambipillai Srikanthan
2015 J jnl
Efficient Digit-Serial KA-Based Multiplier Over Binary Extension Fields Using Block Recombination Approach.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chung-Hsin Liu, Chiou-Yng Lee, Pramod Kumar Meher
2015 J jnl
Efficient Subquadratic Space Complexity Architectures for Parallel MPB Single- and Double-Multiplications for All Trinomials Using Toeplitz Matrix-Vector Product Decomposition.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chiou-Yng Lee, Pramod Kumar Meher
2015 J jnl
Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pramod Kumar Meher, Basant Kumar Mohanty, Sujit Kumar Patel, Soumya Ganguly, Thambipillai Srikanthan
2015 C conf
Efficient subquadratic parallel multiplier based on modified SPB of GF(2
ISCAS
Jeng-Shyang Pan, Pramod Kumar Meher, Chiou-Yng Lee, Hong-Hai Bai
2015 J jnl
FPGA Implementation of Orthogonal Matching Pursuit for Compressive Sensing Reconstruction.
IEEE Trans. Very Large Scale Integr. Syst.
Hassan Rabah, Abbes Amira, Basant Kumar Mohanty, Somaya Al-Máadeed, Pramod Kumar Meher
2015 J jnl
Fine-Grained Critical Path Analysis and Optimization for Area-Time Efficient Realization of Multiple Constant Multiplications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xin Lou, Ya Jun Yu, Pramod Kumar Meher
2015 C conf
Fine-grained pipelining for multiple constant multiplications.
ISCAS
Xin Lou, Pramod Kumar Meher, Ya Jun Yu
2015 J jnl
High-Throughput Digit-Level Systolic Multiplier Over GF(2
IEEE Trans. Circuits Syst. II Express Briefs
Jiafeng Xie, Pramod Kumar Meher, Zhi-Hong Mao
2015 J jnl
High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jiafeng Xie, Pramod Kumar Meher, Zhi-Hong Mao
2015 Misc conf
Low-Area and Low-Power Reconfigurable Architecture for Convolution-Based 1-D DWT Using 9/7 and 5/3 Filters.
VLSID
Pramod Kumar Meher, Basant Kumar Mohanty, M. N. S. Swamy
2015 J jnl
Low-Latency High-Throughput Systolic Multipliers Over GF(2
IEEE Trans. Circuits Syst. I Regul. Pap.
Jiafeng Xie, Pramod Kumar Meher, Zhi-Hong Mao
2015 J jnl
New Approach to the Reduction of Sign-Extension Overhead for Efficient Implementation of Multiple Constant Multiplications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xin Lou, Ya Jun Yu, Pramod Kumar Meher
2015 J jnl
Subquadratic Space-Complexity Digit-Serial Multipliers Over GF(2
IEEE Trans. Circuits Syst. I Regul. Pap.
Chiou-Yng Lee, Pramod Kumar Meher
2015 J jnl
Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function Evaluation.
IEEE Trans. Circuits Syst. II Express Briefs
Shen-Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, Pramod Kumar Meher
2014 C conf
A novel DA-based architecture for efficient computation of inner-product of variable vectors.
ISCAS
Pramod Kumar Meher, Sang Yoon Park
2014 J jnl
Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay.
IEEE Trans. Very Large Scale Integr. Syst.
Pramod Kumar Meher, Sang Yoon Park
2014 C conf
Area-delay efficient architecture for MP algorithm using reconfigurable inner-product circuits.
ISCAS
Pramod Kumar Meher, Basant K. Mohanty, Thambipillai Srikanthan
2014 J jnl
Area-delay-power-efficient architecture for folded two-dimensional discrete wavelet transform by multiple lifting computation.
IET Image Process.
Basant K. Mohanty, Pramod Kumar Meher
2014 J jnl
Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yu Pan, Pramod Kumar Meher
2014 J jnl
Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pramod Kumar Meher, Sang Yoon Park
2014 J jnl
Efficient $M$ -ary Exponentiation over $GF(2^{m})$ Using Subquadratic KA-Based Three-Operand Montgomery Multiplier.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chiou-Yng Lee, Pramod Kumar Meher, Chien-Ping Chang
2014 J jnl
Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter.
IEEE Trans. Circuits Syst. II Express Briefs
Sang Yoon Park, Pramod Kumar Meher
2014 J jnl
Efficient Integer DCT Architectures for HEVC.
IEEE Trans. Circuits Syst. Video Technol.
Pramod Kumar Meher, Sang Yoon Park, Basant Kumar Mohanty, Khoon Seong Lim, Chuohao Yeo
2014 C conf
High-speed multiplier block design based on bit-level critical path optimization.
ISCAS
Xin Lou, Ya Jun Yu, Pramod Kumar Meher
2014 J jnl
Low-Complexity Digit-Serial and Scalable SPB/GPB Multipliers Over Large Binary Extension Fields Using (b, 2)-Way Karatsuba Decomposition.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chiou-Yng Lee, Chun-Sheng Yang, Bimal Kumar Meher, Pramod Kumar Meher, Jeng-Shyang Pan
2014 J jnl
Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite Impulse Response Filters.
IEEE Trans. Circuits Syst. I Regul. Pap.
Basant K. Mohanty, Pramod Kumar Meher, Somaya Al-Máadeed, Abbes Amira
2014 C conf
Reconfigurable CORDIC architectures for multi-mode and multi-trajectory operations.
ISCAS
Supriya Aggarwal, Pramod Kumar Meher
2014 — conf
Subquadratic space complexity digit-serial multiplier over binary extension fields using Toom-Cook algorithm.
ISIC
Chiou-Yng Lee, Pramod Kumar Meher, Wen-Yo Lee
2013 J jnl
A High-Performance Energy-Efficient Architecture for FIR Adaptive Filter Based on New Distributed Arithmetic Formulation of Block LMS Algorithm.
IEEE Trans. Signal Process.
Basant K. Mohanty, Pramod Kumar Meher
2013 — conf
A fast 8×8 integer Tchebichef transform and comparison with integer cosine transform for image compression.
MWSCAS
Soni Prattipati, Sujata Ishwar, M. N. S. Swamy, Pramod Kumar Meher
2013 C conf
A variable quantization technique for image compression using integer Tchebichef transform.
ICICS
Soni Prattipati, M. N. S. Swamy, Pramod Kumar Meher
2013 J jnl
An Efficient Look-up Table-based Approach for Multiplication over GF(2
Circuits Syst. Signal Process.
Bimal Kumar Meher, Pramod Kumar Meher
2013 J jnl
CORDIC Designs for Fixed Angle of Rotation.
IEEE Trans. Very Large Scale Integr. Syst.
Pramod Kumar Meher, Sang Yoon Park
2013 C conf
Flexible integer DCT architectures for HEVC.
ISCAS
Sang Yoon Park, Pramod Kumar Meher
2013 J jnl
Guest Editorial: Advanced Techniques for Efficient Electronic System Design.
Circuits Syst. Signal Process.
Pramod Kumar Meher, Saraju P. Mohanty, A. Prasad Vinod
2013 J jnl
Hardware-Efficient Realization of Prime-Length DCT Based on Distributed Arithmetic.
IEEE Trans. Computers
Jiafeng Xie, Pramod Kumar Meher, Jianjun He
2013 J jnl
Low Latency Systolic Montgomery Multiplier for Finite Field $GF(2^{m})$ Based on Pentanomials.
IEEE Trans. Very Large Scale Integr. Syst.
Jiafeng Xie, Jianjun He, Pramod Kumar Meher
2013 J jnl
Low-Complexity Multiplier for GF(2
IEEE Trans. Very Large Scale Integr. Syst.
Jiafeng Xie, Pramod Kumar Meher, Jianjun He
2013 J jnl
Low-Latency Digit-Serial and Digit-Parallel Systolic Multipliers for Large Binary Extension Fields.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jeng-Shyang Pan, Chiou-Yng Lee, Pramod Kumar Meher
2013 J jnl
Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic.
IEEE Trans. Circuits Syst. II Express Briefs
Sang Yoon Park, Pramod Kumar Meher
2013 J jnl
Memory-Efficient High-Speed Convolution-Based Generic Structure for Multilevel 2-D DWT.
IEEE Trans. Circuits Syst. Video Technol.
Basant K. Mohanty, Pramod Kumar Meher
2013 J jnl
Scale-Free Hyperbolic CORDIC Processor and Its Application to Waveform Generation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Supriya Aggarwal, Pramod Kumar Meher, Kavita Khare
2013 J jnl
Special section on image and video processing for security.
Signal Image Video Process.
Natarajan Sudha, Niladri B. Puhan, Pramod Kumar Meher
2013 J jnl
Zero-quantised discrete cosine transform coefficients prediction technique for intra-frame video encoding.
IET Image Process.
Maher Jridi, Pramod Kumar Meher, Ayman Alfalou
2012 Misc conf
A low-complexity spectrum sensing technique for cognitive radios based on correlation of intra-segment decimated vectors.
ICCS
Syed Naveen Altaf Ahmed, Pramod Kumar Meher, A. Prasad Vinod
2012 J jnl
Area- and Power-Efficient Architecture for High-Throughput Implementation of Lifting 2-D DWT.
IEEE Trans. Circuits Syst. II Express Briefs
Basant K. Mohanty, Anurag Mahajan, Pramod Kumar Meher
2012 J jnl
Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection.
IEEE Trans. Very Large Scale Integr. Syst.
Supriya Aggarwal, Pramod Kumar Meher, Kavita Khare
2012 C conf
Efficient architectures for VLSI implementation of 2-D discrete Hadamard transform.
ISCAS
Basant K. Mohanty, Pramod Kumar Meher, Subodh Kumar Singhal
2012 J jnl
High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes.
IEEE Trans. Very Large Scale Integr. Syst.
Francisco Garcia-Herrero, María José Canet, Javier Valls, Pramod Kumar Meher
2012 C conf
Low-latency area-delay-efficient systolic multiplier over GF(2
ISCAS
Jiafeng Xie, Pramod Kumar Meher, Jianjun He
2012 J jnl
New encoded single-indicator sequences based on physico-chemical parameters for efficient exon identification.
Int. J. Bioinform. Res. Appl.
Jayakishan Meher, Pramod Kumar Meher, Gananath Dash, Mukesh Kumar Raval
2012 J jnl
Optimized Architecture Using a Novel Subexpression Elimination on Loeffler Algorithm for DCT-Based Image Compression.
VLSI Design
Maher Jridi, Ayman Alfalou, Pramod Kumar Meher
2011 — conf
A New Look-Up Table Approach for High-Speed Finite Field Multiplication.
ISED
Bimal Kumar Meher, Pramod Kumar Meher
2011 J jnl
A Self-Configurable Systolic Architecture for Face Recognition System Based on Principal Component Neural Network.
IEEE Trans. Circuits Syst. Video Technol.
Natarajan Sudha, A. R. Mohan, Pramod Kumar Meher
2011 C conf
A high-speed FIR adaptive filter architecture using a modified delayed LMS algorithm.
ISCAS
Pramod Kumar Meher, Megha Maheshwari
2011 J jnl
Development of Laguerre Neural-Network-Based Intelligent Sensors for Wireless Sensor Networks.
IEEE Trans. Instrum. Meas.
Jagdish Chandra Patra, Pramod Kumar Meher, Goutam Chakraborty
2011 C conf
Efficient coefficient partitioning for decomposed DA-based inner-product computation.
ISCAS
Yu Pan, Pramod Kumar Meher
2011 J jnl
Guest Editorial: Special Issue on Embedded Signal Processing Circuits and Systems for Cognitive Radio-Based Wireless Communication Devices.
Circuits Syst. Signal Process.
A. Prasad Vinod, Edmund Ming-Kit Lai, Pramod Kumar Meher, Jacques Palicot, Shahriar Mirabbasi
2011 J jnl
High-Speed RS(255, 239) Decoder Based on LCC Decoding.
Circuits Syst. Signal Process.
Francisco Garcia-Herrero, Javier Valls, Pramod Kumar Meher
2011 C conf
High-throughput pipelined realization of adaptive FIR filter based on distributed arithmetic.
VLSI-SoC
Pramod Kumar Meher, Sang Yoon Park
2011 J jnl
Improved Comb Filter based Approach for Effective Prediction of Protein Coding Regions in DNA Sequences.
J. Signal Inf. Process.
Jayakishan Meher, Pramod Kumar Meher, Gananath Dash
2011 C conf
MCM-based implementation of block FIR filters for high-speed and low-power applications.
VLSI-SoC
Pramod Kumar Meher, Yu Pan
2011 J jnl
Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT.
IEEE Trans. Signal Process.
Basant K. Mohanty, Pramod Kumar Meher
2011 J jnl
Memory-Efficient Architecture for 3-D DWT Using Overlapped Grouping of Frames.
IEEE Trans. Signal Process.
Basant K. Mohanty, Pramod Kumar Meher
2011 — conf
Speeding up Subquadratic Finite Field Multiplier over GF(2m) Generated by Trinomials Using Toeplitz Matrix-Vector with Inner Product Formula.
ICGEC
Chiou-Yng Lee, Pramod Kumar Meher
2011 J jnl
The Role of Combined OSR and SDF Method for Pre-Processing of Microarray Data that Accounts for Effective Denoising and Quantification.
J. Signal Inf. Process.
Jayakishan Meher, Mukesh Kumar Raval, Pramod Kumar Meher, Gananath Dash
2010 B conf
An improved SOM-based visualization technique for DNA microarray data analysis.
IJCNN
Jagdish Chandra Patra, Jacob A. Abraham, Pramod Kumar Meher, Goutam Chakraborty
2010 J jnl
An improved common subexpression elimination method for reducing logic operators in FIR filter implementations without increasing logic depth.
Integr.
Achutavarrier Prasad Vinod, Edmund Ming-Kit Lai, Douglas L. Maskell, Pramod Kumar Meher
2010 C conf
An optimized lookup-table for the evaluation of sigmoid function for artificial neural networks.
VLSI-SoC
Pramod Kumar Meher
2010 — conf
Area-efficient parallel-prefix Ling adders.
APCCAS
Tso-Bing Juang, Pramod Kumar Meher, Chung-Chun Kuan
2010 J jnl
Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over GF(2
IEEE Trans. Very Large Scale Integr. Syst.
Chiou-Yng Lee, Pramod Kumar Meher, Jagdish Chandra Patra
2010 B conf
DNA microarray analysis using Equalized Orthogonal Mapping.
IJCNN
Jagdish Chandra Patra, Nyttle V. George, Pramod Kumar Meher
2010 J jnl
Efficient Systolic Designs for 1- and 2-Dimensional DFT of General Transform-Lengths for High-Speed Wireless Communication Applications.
J. Signal Process. Syst.
Pramod Kumar Meher, Jagdish Chandra Patra, Achutavarrier Prasad Vinod
2010 J jnl
Efficient bit-parallel multipliers over finite fields GF(2
Comput. Electr. Eng.
Chiou-Yng Lee, Pramod Kumar Meher
2010 J jnl
LUT Optimization for Memory-Based Computation.
IEEE Trans. Circuits Syst. II Express Briefs
Pramod Kumar Meher
2010 J jnl
New Approach to Look-Up-Table Design and Memory-Based Realization of FIR Digital Filter.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pramod Kumar Meher
2010 C conf
Novel input coding technique for high-precision LUT-based multiplication for DSP applications.
VLSI-SoC
Pramod Kumar Meher
2010 J jnl
Parallel and Pipeline Architectures for High-Throughput Computation of Multilevel 3-D DWT.
IEEE Trans. Circuits Syst. Video Technol.
Basant K. Mohanty, Pramod Kumar Meher
2009 J jnl
50 Years of CORDIC: Algorithms, Architectures, and Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pramod Kumar Meher, Javier Valls, Tso-Bing Juang, K. Sridharan, Koushik Maharatna
2009 — conf
An optimized design for serial-parallel finite field multiplication over
ASP-DAC
Pramod Kumar Meher, Yajun Ha, Chiou-Yng Lee
2009 B conf
Computationally efficient FLANN-based intelligent stock price prediction system.
IJCNN
Jagdish Chandra Patra, Nguyen C. Thanh, Pramod Kumar Meher
2009 J jnl
Efficient CORDIC Algorithms and Architectures for Low Area and High Throughput Implementation.
IEEE Trans. Circuits Syst. II Express Briefs
Leena Vachhani, K. Sridharan, Pramod Kumar Meher
2009 J jnl
Efficient FPGA Realization of CORDIC With Application to Robotic Exploration.
IEEE Trans. Ind. Electron.
Leena Vachhani, K. Sridharan, Pramod Kumar Meher
2009 J jnl
Extended Sequential Logic for Synchronous Circuit Optimization and Its Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pramod Kumar Meher
2009 C conf
New Approach to LUT Implementation and Accumulation for Memory-based Multiplication.
ISCAS
Pramod Kumar Meher
2009 J jnl
Nonlinear channel equalization for wireless communication systems using Legendre neural networks.
Signal Process.
Jagdish Chandra Patra, Pramod Kumar Meher, Goutam Chakraborty
2009 J jnl
On Efficient Implementation of Accumulation in Finite Field Over GF(2
IEEE Trans. Very Large Scale Integr. Syst.
Pramod Kumar Meher
2009 C conf
Scalable Serial-parallel Multiplier over GF(2
ISCAS
Pramod Kumar Meher, Chiou-Yng Lee
2009 J jnl
Systolic and Non-Systolic Scalable Modular Designs of Finite Field Multipliers for Reed-Solomon Codec.
IEEE Trans. Very Large Scale Integr. Syst.
Pramod Kumar Meher
2008 — conf
Concurrent systolic architecture for high-throughput implementation of 3-dimensional discrete wavelet transform.
ASAP
Basant K. Mohanty, Pramod Kumar Meher
2008 B conf
Content-based image retrieval using orthogonal moments heuristically.
SMC
Jagdish Chandra Patra, Sonaabh Sood, Pramod Kumar Meher, Cédric Bornand
2008 B conf
Determination of QSAR of aldose reductase inhibitors using an RBF network.
SMC
Jagdish Chandra Patra, Rowena Wai Sim Cheong, Pramod Kumar Meher, Goutam Chakraborty
2008 B conf
Development of intelligent sensors using Legendre functional-link artificial neural networks.
SMC
Jagdish Chandra Patra, Pramod Kumar Meher, Goutam Chakraborty
2008 C conf
Discrete tchebichef transform-A fast 4x4 algorithm and its application in image/video compression.
ISCAS
Sujata Ishwar, Pramod Kumar Meher, M. N. S. Swamy
2008 C conf
Efficient Bit-Parallel Multipliers in Composite Fields.
APSCC
Chiou-Yng Lee, Pramod Kumar Meher
2008 — conf
Efficient systolization of cyclic convolution for systolic implementation of sinusoidal transforms.
ASAP
Pramod Kumar Meher
2008 J jnl
FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic.
IEEE Trans. Signal Process.
Pramod Kumar Meher, Shrutisagar Chandrasekaran, Abbes Amira
2008 — conf
Fully-pipelined efficient architectures for FPGA realization of discrete Hadamard transform.
ASAP
Pramod Kumar Meher, Jagdish Chandra Patra
2008 J jnl
Hardware-Efficient Systolic-Like Modular Design for Two-Dimensional Discrete Wavelet Transform.
IEEE Trans. Circuits Syst. II Express Briefs
Pramod Kumar Meher, Basant K. Mohanty, Jagdish Chandra Patra
2008 B conf
Legendre-FLANN-based nonlinear channel equalization in wireless communication system.
SMC
Jagdish Chandra Patra, Wei Chiat Chin, Pramod Kumar Meher, Goutam Chakraborty
2008 J jnl
Neural-Network-Based Robust Linearization and Compensation Technique for Sensors Under Nonlinear Environmental Influences.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jagdish Chandra Patra, Goutam Chakraborty, Pramod Kumar Meher
2008 J jnl
New Approach to Scalable Parallel and Pipelined Realization of Repetitive Multiple Accumulations.
IEEE Trans. Circuits Syst. II Express Briefs
Pramod Kumar Meher
2008 J jnl
Parallel and Pipelined Architectures for Cyclic Convolution by Block Circulant Formulation Using Low-Complexity Short-Length Algorithms.
IEEE Trans. Circuits Syst. Video Technol.
Pramod Kumar Meher
2008 B conf
Robust CRT-based watermarking technique for authentication of image and document.
SMC
Jagdish Chandra Patra, Alagappan Karthik, Pramod Kumar Meher, Cédric Bornand
2008 B conf
Support vector machine application in drug discovery of aldose reductase inhibitors.
SMC
Jagdish Chandra Patra, Li Li, Pramod Kumar Meher
2008 J jnl
Systolic and Super-Systolic Multipliers for Finite Field GF(2
IEEE Trans. Circuits Syst. I Regul. Pap.
Pramod Kumar Meher
2008 — conf
Throughput-scalable hybrid-pipeline architecture for multilevel lifting 2-D DWT of JPEG 2000 coder.
ASAP
Basant K. Mohanty, Pramod Kumar Meher
2008 J jnl
WMicaD: A New Digital Watermarking Technique Using Independent Component Analysis.
EURASIP J. Adv. Signal Process.
Thang Viet Nguyen, Jagdish Chandra Patra, Pramod Kumar Meher
2007 B conf
DNA Microarray Data Analysis: Effective Feature Selection for Accurate Cancer Classification.
IJCNN
Jagdish Chandra Patra, Goh P. Lim, Pramod Kumar Meher, Ee Luang Ang
2007 J jnl
High-Throughput Memory-Based Architecture for DHT Using a New Convolutional Formulation.
IEEE Trans. Circuits Syst. II Express Briefs
Pramod Kumar Meher, Jagdish Chandra Patra, M. N. S. Swamy
2007 J jnl
New Systolic Algorithm and Array Architecture for Prime-Length Discrete Sine Transform.
IEEE Trans. Circuits Syst. II Express Briefs
Pramod Kumar Meher, M. N. S. Swamy
2007 — conf
Systolic Formulation for Low-Complexity Serial-Parallel Implementation of Unified Finite Field Multiplication over GF(2
ASAP
Pramod Kumar Meher
2006 — conf
A 2-D Systolic Array for High-Throughput Computation of 2-D Discrete Fourier Transform.
APCCAS
Pramod Kumar Meher, Jagdish Chandra Patra, A. Prasad Vinod
2006 B conf
A New SOM-based Visualization Technique for DNA Microarray Data.
IJCNN
Jagdish Chandra Patra, Ee Luang Ang, Pramod Kumar Meher, Qin Zhen
2006 C conf
A new approach to secure distributed storage, sharing and dissemination of digital image.
ISCAS
Pramod Kumar Meher, Jagdish Chandra Patra
2006 C conf
A novel neural network-based linearization and auto-compensation technique for sensors.
ISCAS
Jagdish Chandra Patra, Ee Luang Ang, Pramod Kumar Meher
2006 — conf
An Improved SVD-Based Watermarking Technique for Image and Document Authentication.
APCCAS
Jagdish Chandra Patra, W. Soh, Ee Luang Ang, Pramod Kumar Meher
2006 J jnl
Efficient Systolic Implementation of DFT Using a Low-Complexity Convolution-Like Formulation.
IEEE Trans. Circuits Syst. II Express Briefs
Pramod Kumar Meher
2006 C conf
Field Programmable Gate Array Implementation of a Neural Network-based Intelligent Sensor System.
ICARCV
Jagdish Chandra Patra, Han Yang Lee, Pramod Kumar Meher, Ee Luang Ang
2006 B conf
Financial Prediction of Major Indices using Computational Efficient Artificial Neural Networks.
IJCNN
Jagdish Chandra Patra, Weineng Lim, Pramod Kumar Meher, Ee Luang Ang
2006 J jnl
Hardware-Efficient Systolization of DA-Based Calculation of Finite Digital Convolution.
IEEE Trans. Circuits Syst. II Express Briefs
Pramod Kumar Meher
2006 J jnl
Highly concurrent reduced-complexity 2-D systolic array for discrete Fourier transform.
IEEE Signal Process. Lett.
Pramod Kumar Meher
2006 — conf
Low Power FIR Filter Realization Using Minimal Difference Coefficients: Part II - Algorithm.
APCCAS
A. Prasad Vinod, Chip-Hong Chang, Pramod Kumar Meher, Ankita Singla
2006 — conf
Low Power FIR Filter Realization using Minimal Difference Coefficients: Part I - Complexity Analysis.
APCCAS
A. Prasad Vinod, Chip-Hong Chang, Pramod Kumar Meher, Ankita Singla
2006 C conf
Low-complexity technique for secure storage and sharing of biomedical images.
ISCAS
Pramod Kumar Meher, Jagdish Chandra Patra, M. R. Meher
2006 — conf
Merged-Cascaded Systolic Array for VLSI Implementation of Discrete Wavelet Transform.
APCCAS
Basant K. Mohanty, Pramod Kumar Meher
2006 — conf
Reduced-Complexity Concurrent Systolic Implementation of the Discrete Sine Transform.
APCCAS
Pramod Kumar Meher, A. Prasad Vinod, Jagdish Chandra Patra, M. N. S. Swamy
2006 J jnl
Scalable and modular memory-based systolic architectures for discrete Hartley transform.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pramod Kumar Meher, Thambipillai Srikanthan, Jagdish Chandra Patra
2006 J jnl
Systolic Designs for DCT Using a Low-Complexity Concurrent Convolutional Formulation.
IEEE Trans. Circuits Syst. Video Technol.
Pramod Kumar Meher
2006 J jnl
Unified Systolic-Like Architecture for DCT and DST Using Distributed Arithmetic.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pramod Kumar Meher
2006 — conf
VLSI Architecture for High-Speed / Low-Power Implementation of Multilevel Lifting DWT.
APCCAS
Basant K. Mohanty, Pramod Kumar Meher
2005 — conf
Area-Time Efficient Systolic Architecture for the DCT.
Asia-Pacific Computer Systems Architecture Conference
Pramod Kumar Meher
2005 J jnl
Design of a fully-pipelined systolic array for flexible transposition-free VLSI of 2-D DFT.
IEEE Trans. Circuits Syst. II Express Briefs
Pramod Kumar Meher
2004 J jnl
WAP-teletext system.
IEEE Trans. Consumer Electron.
Nadarajah Sriskanthan, Pramod Kumar Meher, Geok See Ng, C. K. Heng
2003 — conf
Low-Power Transform-Domain Coding by Separable Two-Dimensional Hartley-Like Transform.
Embedded Systems and Applications
Pramod Kumar Meher, Thambipillai Srikanthan, M. Mahesh Kumar, S. Arunkumar
2002 — conf
Effective communication in ad hoc network of mobile users group.
APCCAS (2)
Prafulla Kumar Behera, Pramod Kumar Meher
2002 — conf
Prospects of Group-Based Communication in Mobile Ad hoc Networks.
IWDC
Prafulla Kumar Behera, Pramod Kumar Meher
2002 — conf
Reconfigurable execution core for high performance DSP applications.
APCCAS (2)
A. K. Rath, Pramod Kumar Meher