Pradip Mandal

72 papers A 2C 2Misc 21Journal 26Unranked 21
YearRankTypeTitle / Venue / Authors
2026 Misc conf
Bipolar Silicon Synapse for Bidirectional Spiking Neural Networks.
VLSID
Tamal Chowdhury, Pradip Mandal
2025 J jnl
An Efficient Measurement Technique Incorporating an Impedimetric Sensor Inside a Phase-Shift-Oscillator Loop.
IEEE Trans. Instrum. Meas.
Suman Biswas, Subhayan Nath, Karabi Biswas, Pradip Mandal
2025 — conf
An Impedimetric Oscillator Based Analog Front-End System and Its Application in PMMA Sensor Based Milk Adulteration Concentration Measurement.
NewCAS
Subhayan Nath, Suman Biswas, Karabi Biswas, Pradip Mandal
2025 Misc conf
Bidirectional Spiking Neuron Based Dual-Mode Signal Acquisition Front-End System.
VLSID
Tamal Chowdhury, Pradip Mandal
2025 — conf
Interconnected Switched-Capacitor Based DC-DC Converters to Enhance Input-to-Output Conversion Range and Driving Capability.
PRIME
Kali Pada Bhukta, Divake Kumar, Pradip Mandal
2024 Misc conf
A Neuro Inspired Pulse Density Modulator Sensing Unipolar and Bipolar Current Signals.
VLSID
Tamal Chowdhury, Pradip Mandal
2024 Misc conf
Use of current-mode and voltage-mode receivers together for on-chip multipoint-to-multipoint data transmission across global interconnects.
VLSID
Jahnvi Singh, Nijwm Wary, Pradip Mandal
2023 C conf
Ultra-low Power Current Comparator.
ISCAS
Subrahmanyam Perumalla, Pradip Mandal
2020 J jnl
Delta-sigma modulator based compact sensor signal acquisition front-end system.
Microelectron. J.
Joydeep Basu, Pradip Mandal
2020 J jnl
Hybrid bidirectional transceiver for multipoint-to-multipoint signalling across on-chip global interconnects.
IET Circuits Devices Syst.
Nijwm Wary, Antroy Roy Chowdhury, Pradip Mandal
2020 J jnl
Switched-Capacitor Common-Mode Feedback-Based Fully Differential Operational Amplifiers and its Usage in Implementation of Integrators.
J. Circuits Syst. Comput.
Joydeep Basu, Pradip Mandal
2019 — conf
A Regulated-Cascode Based Current-Integrating TIA RX with 1-tap Speculative Adaptive DFE.
MWSCAS
Antroy Roy Chowdhury, Nijwm Wary, Pradip Mandal
2019 Misc conf
Energy Efficient Bidirectional Equalized Transceiver with PVT Insensitive Active Termination.
VLSID
Antroy Roy Chowdhury, Nijwm Wary, Pradip Mandal
2019 J jnl
Fast locking, startup-circuit free, low area, 32-phase analog DLL.
Integr.
Sabir Ali Mondal, Pradip Mandal, Hafizur Rahaman
2018 C conf
Effect of Switched-Capacitor CMFB on the Gain of Fully Differential Op-Amp for Design of Integrators.
ISCAS
Joydeep Basu, Pradip Mandal
2018 J jnl
Submanifolds of generalized \((k, \mu )\) -space-forms.
Period. Math. Hung.
Shyamal Kumar Hui, Siraj Uddin, Pradip Mandal
2017 J jnl
Current-Mode Full-Duplex Transceiver for Lossy On-Chip Global Interconnects.
IEEE J. Solid State Circuits
Nijwm Wary, Pradip Mandal
2017 J jnl
Current-Mode Triline Transceiver for Coded Differential Signaling Across On-Chip Global Interconnects.
IEEE Trans. Very Large Scale Integr. Syst.
Nijwm Wary, Pradip Mandal
2016 Misc conf
A Stacked VCO Architecture for Generating Multi-level Synchronous Control Signals.
VLSID
Samiran Dam, Pradip Mandal
2015 J jnl
High-speed energy-efficient bi-directional transceiver for on-chip global interconnects.
IET Circuits Devices Syst.
Nijwm Wary, Pradip Mandal
2015 J jnl
Prediction of reference spur in frequency synthesisers.
IET Circuits Devices Syst.
Debashis Mandal, Pradip Mandal, T. K. Bhattacharyya
2015 J jnl
Spur reduction in frequency synthesizer with an array of switched capacitors.
Int. J. Circuit Theory Appl.
Debashis Mandal, Pradip Mandal, Tarun Kanti Bhattacharyya
2014 J jnl
An approach to design and implementation of on-chip clock generator for the switched capacitor based embedded DC-DC converter.
Comput. Electr. Eng.
Kaushik Bhattacharyya, Pradip Mandal
2014 J jnl
ISGP: Iterative sequential geometric programming for precise and robust CMOS analog circuit sizing.
Integr.
Sudip Kundu, Pradip Mandal
2014 J jnl
Spur reducing architecture of frequency synthesiser using switched capacitors.
IET Circuits Devices Syst.
Debashis Mandal, Pradip Mandal, T. K. Bhattacharyya
2013 J jnl
Modeling and design of CMOS analog circuits through hierarchical abstraction.
Integr.
Samiran Dam, Pradip Mandal
2012 Misc conf
A Fast Equation Free Iterative Approach to Analog Circuit Sizing.
VLSI Design
Supriyo Maji, Pradip Mandal
2012 J jnl
A High Performance Switched Capacitor-Based DC-DC Buck Converter Suitable for Embedded Power Management Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Biswajit Maity, Pradip Mandal
2012 J jnl
A Low-Power 5-Gb/s Current-Mode LVDS Output Driver and Receiver with Active Termination.
Circuits Syst. Signal Process.
Vijaya Sankara Rao Pasupureddi, Nachiket V. Desai, Pradip Mandal
2012 J jnl
Active-terminated transmitter and receiver circuits for high-speed low-swing duobinary signaling.
Int. J. Circuit Theory Appl.
Vijaya Sankara Rao Pasupureddi, Pradip Mandal
2012 J jnl
Design and Implementation of an Area and Power Efficient Switched-Capacitor Based Embedded DC-DC Converter.
J. Low Power Electron.
Biswajit Maity, Soumya Gangula, Pradip Mandal
2012 — conf
Design of Push-Pull Dynamic Leaker Circuit for a Low Power Embedded Voltage Regulator.
VDAT
Biswajit Maity, Pradip Mandal
2012 — conf
Effcient approaches to overcome non-convexity issues in analog design automation.
ISQED
Supriyo Maji, Pradip Mandal
2012 J jnl
Improvement of Performance of Dynamically Reconfigurable Switched Capacitor Based Non-Overlap Rotational Time Interleaved Embedded DC-DC Converter.
J. Low Power Electron.
Kaushik Bhattacharyya, Pradip Mandal
2012 J jnl
Improvement of Power Efficiency and output voltage Ripple of Embedded DC-DC converters with Three Step Down ratios.
J. Circuits Syst. Comput.
Kaushik Bhattacharyya, P. V. Ratna Kumar, Pradip Mandal
2012 Misc conf
Iterative Performance Model Upgradation in Geometric Programming Based Analog Circuit Sizing for Improved Design Accuracy.
VLSI Design
Samiran Dam, Pradip Mandal
2012 — conf
Spur suppression in frequency synthesizer using switched capacitor array.
ISOCC
Debashis Mandal, Pradip Mandal, Tarun Kanti Bhattacharyya
2011 — conf
A CAD methodology for automatic topology selection & sizing.
SoCC
Supriyo Maji, Pradip Mandal
2011 Misc conf
A New Double Data Rate(DDR) Dual-Mode Duobinary Transmitter Architecture.
VLSI Design
Mrigank Sharad, Vijaya Sankara Rao Pasupureddi, Pradip Mandal
2011 J jnl
A dynamically reconfigurable NRTI switched-capacitor-based hybrid DC-DC converter suitable for embedded applications.
Microelectron. J.
Kaushik Bhattacharyya, Pradip Mandal
2011 — conf
A geometric programming aided knowledge based approach for analog circuit synthesis and sizing.
ACM Great Lakes Symposium on VLSI
Supriyo Maji, Pradip Mandal
2011 — conf
An automated design methodology for yield aware analog circuit synthesis in submicron technology.
ISQED
Sabyasachi Deyati, Pradip Mandal
2011 — conf
Automatic generation of saturation constraints and performance expressions for geometric programming based analog circuit sizing.
ISQED
Supriyo Maji, Samiran Dam, Pradip Mandal
2011 J jnl
Current-mode full-duplex (CMFD) signaling for high-speed chip-to-chip interconnect.
Microelectron. J.
Vijaya Sankara Rao Pasupureddi, Pradip Mandal
2011 J jnl
Technique for the reduction of output voltage ripple of switched capacitor-based DC??DC converters.
IET Circuits Devices Syst.
Kaushik Bhattacharyya, Pradip Mandal
2010 — conf
A new power efficient current-mode 4-PAM transmitter interface for off-chip interconnect.
APCCAS
Vijaya Sankara Rao Pasupureddi, Pradip Mandal
2010 Misc conf
An Improvised MOS Transistor Model Suitable for Geometric Program Based Analog Circuit Sizing in Sub-micron Technology.
VLSI Design
Samiran Dasgupta, Pradip Mandal
2010 — conf
Current-mode echo cancellation for full-duplex chip-to-chip data communication.
APCCAS
Vijaya Sankara Rao Pasupureddi, Pradip Mandal
2010 Misc conf
On-Chip Inductor-Less DC-DC Boost Converter with Non-overlapped Rotational-Interleaving Scheme.
VLSI Design
Tamal Das, Pradip Mandal
2009 — conf
An automated design approach for CMOS LDO regulators.
ASP-DAC
Samiran Dasgupta, Pradip Mandal
2009 — conf
Circuit Partitioning Using Particle Swarm Optimization for Pseudo-Exhaustive Testing.
ARTCom
S. Krishna Kumar, P. Uday Bhaskar, Santanu Chattopadhyay, Pradip Mandal
2009 — conf
High-Speed Low-Current Duobinary Signaling Over Active Terminated Chip-to-Chip Interconnect.
ISVLSI
Vijaya Sankara Rao Pasupureddi, Pradip Mandal, Sunil Sachdev
2009 A conf
Improvement of power efficiency in switched capacitor DC-DC converter by shoot-through current elimination.
ISLPED
P. V. Ratna Kumar, Kaushik Bhattacharyya, Tamal Das, Pradip Mandal
2009 Misc conf
Switched-Capacitor Based Buck Converter Design Using Current Limiter for Better Efficiency and Output Ripple.
VLSI Design
Tamal Das, Pradip Mandal
2009 J jnl
Switched-Capacitor Based Buck Converter Design Using Current Limiter.
J. Low Power Electron.
Tamal Das, Pradip Mandal
2008 Misc conf
A Low Voltage, Low Ripple, on Chip, Dual Switch-Capacitor Based Hybrid DC-DC Converter.
VLSI Design
Kaushik Bhattacharyya, Pradip Mandal
2008 Misc conf
Integrated TIA-Equalizer for High Speed Optical Link.
VLSI Design
Saurav Bandyopadhyay, Pradip Mandal, Stephen E. Ralph, Kenneth Pedrotti
2007 — conf
A Fractional Frequency Synthesizer Using Frequency Locked Loop.
ICECS
A. V. Rejeesh, Pradip Mandal
2006 Misc conf
An On-Chip Voltage Regulator with Improved Load Regulation and Light Load Power Efficiency.
VLSI Design
R. G. Raghavendra, Pradip Mandal
2006 — conf
Design and Analysis of a VHF OTA-C Cell for Optimum Phase Response.
APCCAS
Kshitij Yadav, Pradip Mandal
2005 — conf
A single circuit solution for voltage sensors.
ISCAS (4)
S. S. Prasad, Pradip Mandal
2005 — conf
High voltage tolerant output buffer design for mixed voltage interfaces.
ISCAS (5)
Debashis Mandal, Pradip Mandal
2005 — conf
Low-power LVDS receiver for 1.3Gbps physical layer (PHY) interface.
ISCAS (3)
Gunjan Mandal, Pradip Mandal
2005 Misc conf
On-Chip Voltage Regulator with Improved Transient Response.
VLSI Design
Ashis Maity, R. G. Raghavendra, Pradip Mandal
2004 Misc conf
A CMOS Beta Multiplier Voltage Reference with Improved Temperature Performance and Silicon Tunability.
VLSI Design
S. S. Prasad, Pradip Mandal
2004 Misc conf
A Narrow Pulse- Suppressing Filter For Input Buffer.
VLSI Design
Pradip Mandal
2004 — conf
Low power LVDS transmitter with low common mode variation for 1GB/s-per pin operation.
ISCAS (1)
Gunjan Mandal, Pradip Mandal
2001 J jnl
CMOS op-amp sizing using a geometric programming formulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pradip Mandal, V. Visvanathan
1999 Misc conf
A New Approach for CMOS Op-Amp Synthesis.
VLSI Design
Pradip Mandal, V. Visvanathan
1997 Misc conf
A Self-Biased High Performance Folded Cascode CMOS Op-Amp.
VLSI Design
Pradip Mandal, V. Visvanathan
1996 Misc conf
Design of high performance two stage CMOS cascode op-amps with stable biasing.
VLSI Design
Pradip Mandal, V. Visvanathan
1993 A conf
Macromodeling of the A.C. characteristics of CMOS Op-amps.
ICCAD
Pradip Mandal, V. Visvanathan