Prabir Saha

18 papers Journal 10Unranked 8
YearRankTypeTitle / Venue / Authors
2024 J jnl
Design of a Novel Inexact 4:2 Compressor and Its Placement in the Partial Product Array for Area, Delay, and Power-Efficient Approximate Multipliers.
Circuits Syst. Signal Process.
Srikant Kumar Beura, Bishnulatpam Pushpa Devi, Prabir Saha, Pramod Kumar Meher
2024 J jnl
Inexact radix-4 Booth multipliers based on new partial product generation scheme for image multiplication.
Integr.
Srikant Kumar Beura, Sudeshna Manjari Mahanta, Bishnulatpam Pushpa Devi, Prabir Saha
2024 — conf
VLSI Implementation of Edge Detection Chip: A Prospective Design.
iSES
Harsh Raj Thakur, Prabir Saha
2022 J jnl
Minimizing Ancilla Inputs and Garbage Outputs of Reversible BCD Multiplier.
J. Circuits Syst. Comput.
Sheba Diamond Thabah, Prabir Saha
2021 — conf
Design and Analysis of Inexact 3: 2 Compressor-based Radix-4 Multiplier towards Image Multiplication.
ICCCNT
Srikant Kumar Beura, Gudmalwar Ashishkumar Prabhakar, Sudesna Manjari Mahanta, Bishnulatpam Pushpa Devi, Prabir Saha
2021 J jnl
Improved Signed Binary Multiplier Through New Partial Product Generation Scheme.
J. Circuits Syst. Comput.
Sheba Diamond Thabah, Prabir Saha
2020 J jnl
A Low Quantum Cost Implementation of Reversible Binary-Coded-Decimal Adder.
Period. Polytech. Electr. Eng. Comput. Sci.
Sheba Diamond Thabah, Prabir Saha
2020 J jnl
Modeling of Short P-Channel Symmetric Double-Gate MOSFET for Low Power Circuit Simulation.
Period. Polytech. Electr. Eng. Comput. Sci.
Rekib Uddin Ahmed, Prabir Saha
2020 J jnl
New design approaches of reversible BCD encoder using Peres and Feynman gates.
ICT Express
Sheba Diamond Thabah, Prabir Saha
2017 — conf
Modeling of Threshold Voltage and Subthreshold Current for P-Channel Symmetric Double-Gate MOSFET in Nanoscale Regime.
iNIS
Rekib Uddin Ahmed, Prabir Saha
2015 — conf
Implementation of high speed processor for computing convolution sum for DSP applications.
IMCOM
Prabir Saha, Deepak Kumar, Abhijit Sharma
2015 — conf
Integer division technique for signal processing applications.
IMCOM
Deepak Kumar, Abhijit Sharma, Prabir Saha
2014 J jnl
Design of 64-Bit Squarer Based on Vedic Mathematics.
J. Circuits Syst. Comput.
Prabir Saha, Deepak Kumar, Partha Bhattacharyya, Anup Dandapat
2014 J jnl
Improved matrix multiplier design for high-speed digital signal processing applications.
IET Circuits Devices Syst.
Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat
2013 — conf
Reciprocal Unit Based on Vedic Mathematics for Signal Processing Applications.
ISED
Prabir Saha, Deepak Kumar, Partha Bhattacharyya, Anup Dandapat
2012 — conf
Design of High Speed Vedic Multiplier for Decimal Number System.
VDAT
Prabir Saha, Arindam Banerjee, Anup Dandapat, Partha Bhattacharyya
2011 J jnl
ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics.
Microelectron. J.
Prabir Saha, Arindam Banerjee, Anup Dandapat, Partha Bhattacharyya
2011 — conf
Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications.
ISED
Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat