Prabhu B. M. Prasad

13 papers Misc 1Journal 7Unranked 5
YearRankTypeTitle / Venue / Authors
2024 J jnl
Object Detection and Classification Framework for Analysis of Video Data Acquired from Indian Roads.
Sensors
Aayushi Padia, Aryan T. N., Sharan Thummagunti, Vivaan Sharma, Manjunath K. Vanahalli, Prabhu B. M. Prasad, G. N. Girish, Yong-Guk Kim, Pavan Kumar B. N.
2021 J jnl
FPGA friendly NoC simulation acceleration framework employing the hard blocks.
Computing
Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar
2020 J jnl
An Efficient FPGA-Based Network-on-Chip Simulation Framework Utilizing the Hard Blocks.
Circuits Syst. Signal Process.
Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar
2020 J jnl
LBNoC: Design of Low-latency Router Architecture with Lookahead Bypass for Network-on-Chip Using FPGA.
ACM Trans. Design Autom. Electr. Syst.
Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar
2020 J jnl
P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA.
Wirel. Pers. Commun.
Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar
2019 J jnl
Analysis of cache behaviour and software optimizations for faster on-chip network simulations.
Int. J. Syst. Assur. Eng. Manag.
Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar
2019 — conf
Design of an Adaptive and Reliable Network on Chip Router Architecture Using FPGA.
VLSI-DAT
Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar
2019 — conf
High-Performance NoC Simulation Acceleration Framework Employing the Xilinx DSP48E1 Blocks.
VLSI-DAT
Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar
2019 — conf
High-Performance NoCs Employing the DSP48E1 Blocks of the Xilinx FPGAs.
ISQED
Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar
2019 J jnl
YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAs.
J. Circuits Syst. Comput.
Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar
2018 — conf
Trace-Driven Simulation and Design Space Exploration of Network-on-Chip Topologies on FPGA.
ISED
G. S. Sangeetha, Vignesh Radhakrishnan, Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar
2018 Misc conf
YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Using FPGAs.
VLSID
Khyamling Parane, Basavaraj Talawar, Prabhu B. M. Prasad
2016 — conf
Cache analysis and software optimizations for faster on-chip network simulations.
ICIIS
Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar