Prab Varma - RankMe

23 papers A* 2A 10Misc 3Journal 4Unranked 4

Year	Rank	Type	Title / Venue / Authors
2016	—	`conf`	Welcome Message. HLDVT Prab Varma, Miroslav N. Velev
2012	—	`conf`	Current and Future Directions in Automatic Test Pattern Generation for Power Delivery Network Validation. Asian Test Symposium Prab Varma
2004	J	`jnl`	Verification evolution or industrial revolution? IEEE Des. Test Comput. Prab Varma
2003	A	`conf`	Design Verification Problems: Test To The Rescue? ITC Prab Varma
2001	Misc	`conf`	ATPG for Design Errors-Is It Possible? VTS Magdy S. Abadir, Scott Davidson, Vijay Nagasamy, Dhiraj K. Pradhan, Prab Varma
2000	J	`jnl`	Test Cycle Count Reduction in a Parallel Scan BIST Environment. J. Electron. Test. Bechir Ayari, Prab Varma
1998	A	`conf`	A structured test re-use methodology for core-based system chips. ITC Prab Varma, Sandeep Bhatia
1998	A*	`conf`	System Chip Test Challenges, Are There Solutions Today? (Panel). DAC Prab Varma
1998	A	`conf`	System chip test: are we there yet? ITC Prab Varma
1998	—	`conf`	Test Cycle Count Reduction in a Parallel Scan BIST Environment. Asian Test Symposium Bechir Ayari, Prab Varma
1997	—	`conf`	Test Compaction in a Parallel Access Scan Environment. Asian Test Symposium Sandeep Bhatia, Prab Varma
1996	A	`conf`	A Unifying Methodology for Intellectual Property and Custom Logic Testing. ITC Sandeep Bhatia, Tushar Gheewala, Prab Varma
1996	Misc	`conf`	Delay Fault Testing: How Robust are Our Models? VTS Sandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma
1995	A	`conf`	Optimizing Product Profitability - The Test Way. ITC Prab Varma
1994	A	`conf`	On Path-Delay Testing in a Standard Scan Environment. ITC Prab Varma
1994	J	`jnl`	The economics of scan-path design for testability. J. Electron. Test. Prab Varma, Tushar Gheewala
1993	A	`conf`	Delay Testing Using a Matrix of Accessible Storage. ITC Prab Varma, Tushar Gheewala
1993	A	`conf`	Scan DFT: Why More Can Cost Less. ITC Prab Varma
1992	Misc	`conf`	On test generation for path delay faults in ASICs. VTS Prab Varma
1990	A	`conf`	TDRC-a symbolic simulation based design for testability rules checker. ITC Prab Varma
1988	J	`jnl`	A knowledge-based test generator for standard cell and iterative array logic circuits. IEEE J. Solid State Circuits Prab Varma, Yoshihiro Tohma
1987	A*	`conf`	A Fast Signature Simulation Tool for Built-In Self-Testing Circuits. DAC S. B. Tan, K. Totton, Keith Baker, Prab Varma, R. Porter
1984	A	`conf`	An Analysis of the Economics of Self Test. ITC Prab Varma, Anthony P. Ambler, Keith Baker