Pouya Houshmand

16 papers A 1B 1C 1Journal 10Unranked 3

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Enabling Efficient Hardware Acceleration of Hybrid Vision Transformer (ViT) Networks at the Edge. CoRR Joren Dumoulin, Pouya Houshmand, Vikram Jain, Marian Verhelst
2025	J	`jnl`	Stream: Design Space Exploration of Layer-Fused DNNs on Heterogeneous Dataflow Accelerators. IEEE Trans. Computers Arne Symons, Linyan Mei, Steven Colleman, Pouya Houshmand, Sebastian Karl, Marian Verhelst
2024	J	`jnl`	Analog or Digital In-memory Computing? Benchmarking through Quantitative Modeling. CoRR Jiacong Sun, Pouya Houshmand, Marian Verhelst
2024	C	`conf`	Enabling Efficient Hardware Acceleration of Hybrid Vision Transformer (ViT) Networks at the Edge. ISCAS Joren Dumoulin, Pouya Houshmand, Vikram Jain, Marian Verhelst
2024	—	`conf`	High-Rate. Compact In-Sensor Denoising for Active Stereo Vision Towards Embedded Depth Sensing. NewCAS Pouya Houshmand, Jean-Sebastien Staelens, Ward van der Tempel, Marian Verhelst
2024	J	`jnl`	Pack my weights and run! Minimizing overheads for in-memory computing accelerators. CoRR Pouya Houshmand, Marian Verhelst
2023	—	`conf`	A 16nm 128kB high-density fully digital In Memory Compute macro with reverse SRAM pre-charge achieving 0.36TOPs/mm ESSCIRC Weijie Jiang, Pouya Houshmand, Marian Verhelst, Wim Dehaene
2023	A	`conf`	Analog or Digital In-Memory Computing? Benchmarking Through Quantitative Modeling. ICCAD Jiacong Sun, Pouya Houshmand, Marian Verhelst
2023	J	`jnl`	Benchmarking and modeling of analog and digital SRAM in-memory computing architectures. CoRR Pouya Houshmand, Jiacong Sun, Marian Verhelst
2023	J	`jnl`	DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge. IEEE J. Solid State Circuits Pouya Houshmand, Giuseppe Maria Sarda, Vikram Jain, Kodai Ueyoshi, Ioannis A. Papistas, Man Shi, Qilin Zheng, Debjyoti Bhattacharjee, Arindam Mallik, Peter Debacker, Diederik Verkest, Marian Verhelst
2023	B	`conf`	Stream: A Modeling Framework for Fine-grained Layer Fusion on Multi-core DNN Accelerators. ISPASS Arne Symons, Linyan Mei, Steven Colleman, Pouya Houshmand, Sebastian Karl, Marian Verhelst
2022	—	`conf`	DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC. ISSCC Kodai Ueyoshi, Ioannis A. Papistas, Pouya Houshmand, Giuseppe Maria Sarda, Vikram Jain, Man Shi, Qilin Zheng, Juan Sebastian Piedrahita Giraldo, Peter Vrancx, Jonas Doevenspeck, Debjyoti Bhattacharjee, Stefan Cosemans, Arindam Mallik, Peter Debacker, Diederik Verkest, Marian Verhelst
2022	J	`jnl`	Towards Heterogeneous Multi-core Accelerators Exploiting Fine-grained Scheduling of Layer-Fused Deep Neural Networks. CoRR Arne Symons, Linyan Mei, Steven Colleman, Pouya Houshmand, Sebastian Karl, Marian Verhelst
2021	J	`jnl`	Hardware-Efficient Residual Neural Network Execution in Line-Buffer Depth-First Processing. IEEE J. Emerg. Sel. Topics Circuits Syst. Man Shi, Pouya Houshmand, Linyan Mei, Marian Verhelst
2021	J	`jnl`	ZigZag: Enlarging Joint Architecture-Mapping Design Space Exploration for DNN Accelerators. IEEE Trans. Computers Linyan Mei, Pouya Houshmand, Vikram Jain, Juan Sebastian Piedrahita Giraldo, Marian Verhelst
2020	J	`jnl`	ZigZag: A Memory-Centric Rapid DNN Accelerator Design Space Exploration Framework. CoRR Linyan Mei, Pouya Houshmand, Vikram Jain, Juan Sebastian Piedrahita Giraldo, Marian Verhelst