Poras T. Balsara

97 papers A* 1A 4B 1C 16Misc 13Journal 43Unranked 19

Year	Rank	Type	Title / Venue / Authors
2024	C	`conf`	Adaptive PLL-based Sensorless Control for CSI-Fed PMSM Drives Used in Submersible Pumps. IECON Milad Bahrami-Fard, Majid Ghasemi Korrani, Mohammad Rastegar, Poras T. Balsara, Babak Fahimi
2024	C	`conf`	Bifurcation Analysis under Various Modulation Techniques in PWM-Controlled DC-DC Converters. IECON Mohammad Hassan Ghaderi, Milad Bahrami-Fard, Nasim Rashidirad, Babak Fahimi, Poras T. Balsara
2024	C	`conf`	Dynamic Modeling of a Double-Stator Switched Reluctance Motor (DSSRM) Using a Lumped Parameter Circuit Model. IECON Behnam Mosammam, Milad Bahrami-Fard, Babak Fahimi, Poras T. Balsara
2024	Misc	`conf`	Hardware-based Detection of Malicious Firmware Modification in Microgrids. VLSID Amisha Srivastava, Sneha Thakur, Abraham Peedikayil Kuruvila, Poras T. Balsara, Kanad Basu
2024	J	`jnl`	Intelligent Multi-Functional Fault Current Limiter. IEEE Trans. Smart Grid Hesam Nourmohamadi, Ghanshyamsinh Gohil, Poras T. Balsara
2023	C	`conf`	Fully Distributed Control of Microgrids Using Multi-Agent Approach. IECON Vaibhav Uttam Pawaskar, Poras T. Balsara, Babak Fahimi, Ghanshyamsinh Gohil
2022	C	`conf`	A new submodule structure with parallel capacitor connection in modular multilevel converters. ISCAS G. Veera Bharath, Ghanshyamsinh Gohil, Poras T. Balsara
2020	J	`jnl`	New Concept for Fault Current Limiter With Voltage Restoration Capability. IEEE Trans. Ind. Electron. Hesam Nourmohamadi, Mehran Sabahi, Poras T. Balsara, Ebrahim Babaei, Seyed Hossein Hosseini, Amir Fakhim-Babaei
2018	J	`jnl`	Mitigation of Positive Zero Effect on Nonminimum Phase Boost DC-DC Converters in CCM. IEEE Trans. Ind. Electron. Vikas V. Paduvalli, R. J. Taylor, Louis R. Hunt, Poras T. Balsara
2017	J	`jnl`	Analysis of Zeros in a Boost DC-DC Converter: State Diagram Approach. IEEE Trans. Circuits Syst. II Express Briefs Vikas V. Paduvalli, R. J. Taylor, Poras T. Balsara
2017	C	`conf`	Portable impedance measurement device for sweat based glucose detection. BSN Athul Asokan Thulasi, Dinesh Bhatia, Poras T. Balsara, Shalini Prasad
2017	J	`jnl`	Time-Domain Analysis of Passive Mixer Impedance: A Switched-Capacitor Approach. IEEE Trans. Circuits Syst. I Regul. Pap. Essam S. Atalla, Frank Zhang, Poras T. Balsara, Abdellatif Bellaouar, Seydou Ba, Kamran Kiasaleh
2016	J	`jnl`	A Digitally Controlled Injection-Locked Oscillator With Fine Frequency Resolution. IEEE J. Solid State Circuits Imran Bashir, Robert Bogdan Staszewski, Poras T. Balsara
2016	J	`jnl`	A Wideband Digital-to-Frequency Converter with Built-In Mechanism for Self-Interference Mitigation. J. Electron. Test. Imran Bashir, Robert Bogdan Staszewski, Oren E. Eliezer, Poras T. Balsara
2016	C	`conf`	Effect of sampling time and sampling instant on the frequency response of a boost converter. IECON Sameer Arora, Poras T. Balsara, Dinesh K. Bhatia
2015	J	`jnl`	Envelope tracking using transient waveform switching shaping supply modulation. Int. J. Circuit Theory Appl. Sankalp Modi, Poras T. Balsara, Oren E. Eliezer
2015	J	`jnl`	Minimum Phase Wide Output Range Digitally Controlled SIDO Boost Converter. IEEE Trans. Circuits Syst. I Regul. Pap. Sujan K. Manohar, L. R. Hunt, Poras T. Balsara, Dinesh K. Bhatia, Vikas V. Paduvalli
2014	J	`jnl`	Complex QR Decomposition Using Fast Plane Rotations for MIMO Applications. IEEE Commun. Lett. Aditya Awasthi, Rohit Guttal, Naofal Al-Dhahir, Poras T. Balsara
2013	—	`conf`	94.6% peak efficiency DCM buck converter with fast adaptive dead-time control. ESSCIRC Sujan K. Manohar, Poras T. Balsara
2013	—	`conf`	Estimation of passive mixer output bandwidth using switched-capacitor techniques. CICC Essam S. Atalla, Frank Zhang, Abdellatif Bellaouar, Poras T. Balsara
2013	—	`conf`	IIP2 requirements in 4G LTE handset receivers. MWSCAS Essam S. Atalla, Abdellatif Bellaouar, Poras T. Balsara
2013	—	`conf`	Novel analysis of passive mixer output impedance using switched-capacitor techniques. MWSCAS Essam S. Atalla, Abdellatif Bellaouar, Poras T. Balsara
2012	—	`conf`	Alien crosstalk mitigation in vectored DSL systems for backhaul applications. ICC Aditya Awasthi, Naofal Al-Dhahir, Oren E. Eliezer, Poras T. Balsara
2012	Misc	`conf`	Bidirectional Single-Supply Level Shifter with Wide Voltage Range for Efficient Power Management. VLSI Design Sujan K. Manohar, Vinod K. Somasundar, Ramakrishnan Venkatasubramanian, Poras T. Balsara
2012	Misc	`conf`	Hybrid NEMS-CMOS DC-DC Converter for Improved Area and Power Efficiency. VLSI Design Sujan K. Manohar, Ramakrishnan Venkatasubramanian, Poras T. Balsara
2012	J	`jnl`	Linear Time-Variant Modeling and Analysis of All-Digital Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. Ioannis L. Syllaios, Poras T. Balsara
2011	J	`jnl`	A Novel Approach for Mitigation of RF Oscillator Pulling in a Polar Transmitter. IEEE J. Solid State Circuits Imran Bashir, Robert Bogdan Staszewski, Oren E. Eliezer, Bhaskar Banerjee, Poras T. Balsara
2011	—	`conf`	Improving performance of NEM relay logic circuits using integrated charge-boosting flip flop. NANOARCH Ramakrishnan Venkatasubramanian, Sujan K. Manohar, Poras T. Balsara
2011	C	`conf`	Multi-clock domain analysis and modeling of all-digital frequency synthesizers. ISCAS Ioannis L. Syllaios, Poras T. Balsara
2010	J	`jnl`	A Generic Scalable Architecture for Min-Sum/Offset-Min-Sum Unit for Irregular/Regular LDPC Decoder. IEEE Trans. Very Large Scale Integr. Syst. Venkata K. Kidambi Srinivasan, Chitranjan K. Singh, Poras T. Balsara
2010	J	`jnl`	An Efficient Linearization Scheme for a Digital Polar EDGE Transmitter. IEEE Trans. Circuits Syst. II Express Briefs Jaimin Mehta, Vasile Zoicas, Oren E. Eliezer, Robert Bogdan Staszewski, Sameh Rezeq, Mitch Entezari, Poras T. Balsara
2010	—	`conf`	Application Specific Instruction Accelerator for Multistandard Viterbi and Turbo Decoding. ICPP Workshops Mangesh K. Kunchamwar, Durga P. Prasad, Pawan Hegde, Poras T. Balsara, Rama Sangireddy
2010	—	`conf`	Design of a link-controller architecture for multiple serial link protocols. SoCC Lei Wang, Pawankumar Hegde, Vishal Nawathe, Roman Staszewski, Poras T. Balsara, Vojin G. Oklobdzija
2010	J	`jnl`	Recombination of Envelope and Phase Paths in Wideband Polar Transmitters. IEEE Trans. Circuits Syst. I Regul. Pap. Ioannis L. Syllaios, Poras T. Balsara, Robert Bogdan Staszewski
2009	J	`jnl`	A Phase Domain Approach for Mitigation of Self-Interference in Wireless Transceivers. IEEE J. Solid State Circuits Oren Eytan Eliezer, Robert Bogdan Staszewski, Imran Bashir, Sumeer Bhatara, Poras T. Balsara
2009	J	`jnl`	All Digital-Quadrature-Modulator Based Wideband Wireless Transmitters. IEEE Trans. Circuits Syst. I Regul. Pap. Viral K. Parikh, Poras T. Balsara, Oren E. Eliezer
2009	J	`jnl`	Parallel Correction and Adaptation Engines for I/Q Mismatch Compensation. IEEE Trans. Circuits Syst. II Express Briefs Imtinan Elahi, Khurram Muhammad, Poras T. Balsara
2008	J	`jnl`	Time-Domain Modeling of an RF All-Digital PLL. IEEE Trans. Circuits Syst. II Express Briefs Ioannis L. Syllaios, Robert Bogdan Staszewski, Poras T. Balsara
2007	C	`conf`	A Low Area and Low Power Digital Band-Pass Sigma-Delta Modulator for Wireless Transmitters. ISCAS Viral K. Parikh, Poras T. Balsara, Oren E. Eliezer, Jaimin Mehta
2007	C	`conf`	A Low Power and Low Quantization Noise Digital Sigma-Delta Modulator for Wireless Transmitters. ISCAS Viral K. Parikh, Poras T. Balsara, Oren E. Eliezer, Jaimin Mehta
2007	J	`jnl`	All-Digital PLL With Ultra Fast Settling. IEEE Trans. Circuits Syst. II Express Briefs Robert Bogdan Staszewski, Poras T. Balsara
2007	C	`conf`	Effect of Word-length Precision on the Performance of MIMO Systems. ISCAS Chitranjan K. Singh, Naofal Al-Dhahir, Poras T. Balsara
2007	—	`conf`	Iterative (TURBO) IQ Imbalance Estimation and Correction in BICM-ID for Flat Fading Channels. VTC Fall Raghunath Cherukuri, Poras T. Balsara
2007	B	`conf`	On the Reconfigurability of All-Digital Phase-Locked Loops for Software Defined Radios. PIMRC Ioannis L. Syllaios, Poras T. Balsara, Robert Bogdan Staszewski
2007	—	`conf`	Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications. CICC Ioannis L. Syllaios, Poras T. Balsara, Robert Bogdan Staszewski
2007	Misc	`conf`	VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition. VLSI Design Chitranjan K. Singh, Sushma Honnavara Prasad, Poras T. Balsara
2006	J	`jnl`	1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Robert Bogdan Staszewski, Sudheer K. Vemulapalli, Prasant Vallur, John L. Wallberg, Poras T. Balsara
2006	Misc	`conf`	A Wide-Range, High-Resolution, Compact CMOS, Time to Digital Converter. VLSI Design V. Ramakrishnan, Poras T. Balsara
2006	C	`conf`	A generalized signal reconstruction method for designing interpolation filters. ISCAS Ioannis L. Syllaios, Poras T. Balsara, Oren E. Eliezer
2006	Misc	`conf`	Exploring Logic Block Granularity in Leakage Tolerant FPGA. VLSI Design Rajan Konar, Rajarshee P. Bharadwaj, Dinesh Bhatia, Poras T. Balsara
2006	—	`conf`	Generic Network Interfaces for Plug and Play NoC Based Architecture. ARC Sanjay Pratap Singh, Shilpa Bhoj, Dheera Balasubramanian, Tanvi Nagda, Dinesh Bhatia, Poras T. Balsara
2006	J	`jnl`	I/Q mismatch compensation using adaptive decorrelation in a low-IF receiver in 90-nm CMOS process. IEEE J. Solid State Circuits Imtinan Elahi, Khurram Muhammad, Poras T. Balsara
2006	J	`jnl`	IIP2 and DC Offsets in the Presence of Leakage at LO Frequency. IEEE Trans. Circuits Syst. II Express Briefs Imtinan Elahi, Khurram Muhammad, Poras T. Balsara
2006	C	`conf`	Reconfigurable CAM Architecture for Network Search Engines. ICCD Mehrdad Nourani, Deepak S. Vijayasarathi, Poras T. Balsara
2005	A	`conf`	Design and Implementation of Configurable W-CDMA Rake Receiver Architectures on FPGA. IPDPS Mukesh Chugh, Dinesh Bhatia, Poras T. Balsara
2005	J	`jnl`	Direct frequency modulation of an ADPLL for bluetooth/GSM with injection pulling elimination. IEEE Trans. Circuits Syst. II Express Briefs Robert Bogdan Staszewski, Dirk Leipold, Poras T. Balsara
2005	J	`jnl`	Event-driven Simulation and modeling of phase noise of an RF oscillator. IEEE Trans. Circuits Syst. I Regul. Pap. Robert Bogdan Staszewski, Chan Fernando, Poras T. Balsara
2005	—	`conf`	Exploiting temporal idleness to reduce leakage power in programmable architectures. ASP-DAC Rajarshee P. Bharadwaj, Rajan Konar, Poras T. Balsara, Dinesh Bhatia
2005	—	`conf`	FPGA Architecture for Standby Power Management. FPT Rajarshee P. Bharadwaj, Rajan Konar, Dinesh Bhatia, Poras T. Balsara
2005	J	`jnl`	Phase-domain all-digital phase-locked loop. IEEE Trans. Circuits Syst. II Express Briefs Robert Bogdan Staszewski, Poras T. Balsara
2005	Misc	`conf`	Power Switch Network Design for MTCMOS. VLSI Design Ramaprasath Vilangudipitchai, Poras T. Balsara
2005	C	`conf`	Ripple-Precharge TCAM A Low-Power Solution for Network Search Engines. ICCD Deepak S. Vijayasarathi, Mehrdad Nourani, Mohammad J. Akhbarizadeh, Poras T. Balsara
2005	J	`jnl`	SoC with an integrated DSP and a 2.4-GHz RF transmitter. IEEE Trans. Very Large Scale Integr. Syst. Robert Bogdan Staszewski, Roman Staszewski, John L. Wallberg, Tom Jung, Chih-Ming Hung, Jinseok Koh, Dirk Leipold, Kenneth Maggio, Poras T. Balsara
2005	Misc	`conf`	The Impact of Inductance on Transients Affecting Gate Oxide Reliability. VLSI Design N. S. Nagaraj, William R. Hunter, Poras T. Balsara, Cyrus D. Cantrell
2005	—	`conf`	VHDL Simulation and Modeling of an All-Digital RF Transmitter. IWSOC Robert Bogdan Staszewski, Roman Staszewski, Poras T. Balsara
2004	J	`jnl`	All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS. IEEE J. Solid State Circuits Robert Bogdan Staszewski, Khurram Muhammad, Dirk Leipold, Chih-Ming Hung, Yo-Chuol Ho, John L. Wallberg, Chan Fernando, Ken Maggio, Roman Staszewski, Tom Jung, Jinseok Koh, Soji John, Irene Yuanying Deng, Vivek Sarda, Oscar Moreira-Tamayo, Valerian Mayega, Ran Katz, Ofer Friedman, Oren Eytan Eliezer, Elida de-Obaldia, Poras T. Balsara
2004	—	`conf`	Event-driven simulation and modeling of an RF oscillator. ISCAS (4) Robert Bogdan Staszewski, Chan Fernando, Poras T. Balsara
2004	Misc	`conf`	Interconnect Modeling for Copper/Low-k Technologies. VLSI Design N. S. Nagaraj, Tom Bonifield, Abha Singh, Roger Griesmer, Poras T. Balsara
2004	C	`conf`	PCAM: A Ternary CAM Optimized for Longest Prefix Matching Tasks. ICCD Mohammad J. Akhbarizadeh, Mehrdad Nourani, Deepak S. Vijayasarathi, Poras T. Balsara
2003	—	`conf`	Benchmarks for Interconnect Parasitic Resistance and Capacitance. ISQED N. S. Nagaraj, Tom Bonifield, Abha Singh, Frank Cano, Usha Narasimha, Mak Kulkarni, Poras T. Balsara, Cyrus D. Cantrell
2003	J	`jnl`	Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process. IEEE Trans. Circuits Syst. II Express Briefs Robert Bogdan Staszewski, Dirk Leipold, Khurram Muhammad, Poras T. Balsara
2003	J	`jnl`	Just-in-time gain estimation of an RF digitally-controlled oscillator for digital direct frequency modulation. IEEE Trans. Circuits Syst. II Express Briefs Robert Bogdan Staszewski, Dirk Leipold, Poras T. Balsara
2002	—	`conf`	Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification. ASP-DAC/VLSI Design N. S. Nagaraj, Poras T. Balsara, Cyrus D. Cantrell
2001	—	`conf`	Challenges in integrated CMOS transceivers for short distance wireless. ACM Great Lakes Symposium on VLSI Khurram Muhammad, Robert Bogdan Staszewski, Poras T. Balsara
2001	Misc	`conf`	Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations. VLSI Design Nagaraj Ns, Poras T. Balsara, Cyrus D. Cantrell
2001	J	`jnl`	Speed, power, area, and latency tradeoffs in adaptive FIR filtering for PRML read channels. IEEE Trans. Very Large Scale Integr. Syst. Khurram Muhammad, Robert Bogdan Staszewski, Poras T. Balsara
2000	J	`jnl`	A 550-MSample/s 8-Tap FIR digital filter for magnetic recording read channels. IEEE J. Solid State Circuits Robert Bogdan Staszewski, Khurram Muhammad, Poras T. Balsara
2000	J	`jnl`	High-performance energy-efficient D-flip-flop circuits. IEEE Trans. Very Large Scale Integr. Syst. Uming Ko, Poras T. Balsara
2000	A	`conf`	Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels. ISLPED Khurram Muhammad, Robert Bogdan Staszewski, Poras T. Balsara
2000	Misc	`conf`	Reconfigurable Array Media Processor (RAMP). FCCM Kamlesh Rath, Sirisha Tangirala, Patrick Friel, Poras T. Balsara, Jose Flores, John P. Wadley
1999	J	`jnl`	High performance low power array multiplier using temporal tiling. IEEE Trans. Very Large Scale Integr. Syst. Shivaling S. Mahant-Shetti, Poras T. Balsara, Carl Lemonds
1999	Misc	`conf`	Mini-Tutorial: Bridging the Gap between TCAD and ECAD Methodologies in Deep Sub-Micron Interconnect Extraction and Analysis. VLSI Design Nagaraj Ns, Poras T. Balsara, Cyrus D. Cantrell
1998	J	`jnl`	Energy optimization of multilevel cache architectures for RISC and CISC processors. IEEE Trans. Very Large Scale Integr. Syst. Uming Ko, Poras T. Balsara, Ashwini K. Nanda
1998	A*	`conf`	LAPLUS: An Efficient, Effective and Stable Switch Algorithm for Flow Control of the Available Bit Rate ATM Service. INFOCOM Sharat Prasad, Kamran Kiasaleh, Poras T. Balsara
1996	A	`conf`	Design techniques for high performance, energy efficient control logic. ISLPED Uming Ko, Anthony M. Hill, Poras T. Balsara
1996	A	`conf`	Leap frog multiplier. ISLPED Shivaling S. Mahant-Shetti, Carl Lemonds, Poras T. Balsara
1996	J	`jnl`	Performance of CMOS differential circuits. IEEE J. Solid State Circuits Pius Ng, Poras T. Balsara, Don Steiss
1995	J	`jnl`	An architecture for a DSP field-programmable gate array. IEEE Trans. Very Large Scale Integr. Syst. M. Agarwala, Poras T. Balsara
1995	—	`conf`	Energy optimization of multi-level processor cache architectures. ISLPD Uming Ko, Poras T. Balsara, Ashwini K. Nanda
1995	J	`jnl`	Hierarchy embedded differential image for progressive transmission using lossless compression. IEEE Trans. Circuits Syst. Video Technol. Whoi-Yul Kim, Poras T. Balsara, David T. Harper III, Jon Wong Park
1995	J	`jnl`	Short-circuit power driven gate sizing technique for reducing power dissipation. IEEE Trans. Very Large Scale Integr. Syst. Uming Ko, Poras T. Balsara
1992	J	`jnl`	Design and implementation of a multi-microprocessor architecture for image processing. Microprocess. Microsystems Arun Vaidyanathan, Eric M. Dowling, Poras T. Balsara
1992	J	`jnl`	Intermediate-level vision tasks on a memory array architecture. Mach. Vis. Appl. Poras T. Balsara, Mary Jane Irwin
1991	J	`jnl`	Digit Serial Multipliers. J. Parallel Distributed Comput. Poras T. Balsara, Robert Michael Owens, Mary Jane Irwin
1991	J	`jnl`	Image processing on a memory array architecture. J. VLSI Signal Process. Poras T. Balsara, Mary Jane Irwin
1987	C	`conf`	Systolic & semi-systolic digit serial multipliers. IEEE Symposium on Computer Arithmetic Poras T. Balsara, Robert Michael Owens
1986	Misc	`conf`	Design and implementation of real time video processor. ICASSP Shishpal Rawat, Poras T. Balsara, Mary Jane Irwin, Tom Mackowiak