Pooya Torkzadeh

20 papers Journal 17Unranked 3
YearRankTypeTitle / Venue / Authors
2025 J jnl
Design and Implementation of a 16-bit Multi-mode 4-Channel Time-Interleaved Delta-Sigma Modulator with SNDR > 106 dB and DCE Compensation Based on FPGA.
Circuits Syst. Signal Process.
Abolfazl Roshanpanah, Pooya Torkzadeh, Khosrow Hajsadeghi, Massoud Dousti
2025 J jnl
Novel hybrid TFET-FinFET 12T SRAM cells with enhanced write margin and read performance.
Integr.
Seyed Arman Sabaghpour, Behzad Ebrahimi, Pooya Torkzadeh
2024 J jnl
A Novel Design of 16-bit Multi-Mode 4-Channel Time-Interleaved Delta-Sigma Digital-to-Analog Converter.
J. Circuits Syst. Comput.
Abolfazl Roshanpanah, Pooya Torkzadeh, Khosrow Hajsadeghi, Massoud Dousti
2023 J jnl
A 256 × 256 CMOS image sensor with differential readout and data converter circuits.
Int. J. Circuit Theory Appl.
Khadijeh Karamzadeh, Masood Teymouri, Massoud Dousti, Pooya Torkzadeh
2022 J jnl
An 8 bits, RF UHF-Band DAC based on interleaved bandpass delta sigma modulator assisted by background digital calibration.
Integr.
Farshad Aghasharif, Mohammadreza Malekpour, Reza Bigdeli, Pooya Torkzadeh
2022 J jnl
Introducing scalable 1-bit full adders for designing quantum-dot cellular automata arithmetic circuits.
Frontiers Inf. Technol. Electron. Eng.
Hamideh Khajehnasir-Jahromi, Pooya Torkzadeh, Massoud Dousti
2021 J jnl
A 6-Bit 1.5-GS/s SAR ADC With Smart Speculative Two-Tap Embedded DFE in 130-nm CMOS for Wireline Receiver Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Azad Mahmoudi, Pooya Torkzadeh, Massoud Dousti
2021 J jnl
Designing a Low-Power LNA and Filter for Portable EEG Acquisition Applications.
IEEE Access
Marzieh Moradi, Massoud Dousti, Pooya Torkzadeh
2020 J jnl
An Ultra-Low-Power, 16 Bits CT Delta-Sigma Modulator Using 4-Bit Asynchronous SAR Quantizer for Medical Applications.
J. Circuits Syst. Comput.
Sahel Javahernia, Esmaeil Najafi Aghdam, Pooya Torkzadeh
2020 J jnl
Fast-Transient-Response Low-Voltage Integrated, Interleaved DC-DC Converter for Implantable Devices.
J. Circuits Syst. Comput.
Najmeh Cheraghi Shirazi, Abumoslem Jannesari, Pooya Torkzadeh
2020 J jnl
Modification and hardware implementation of cortex-like object recognition model.
IET Image Process.
Alireza Mohammadi Anbaran, Pooya Torkzadeh, Reza Ebrahimpour, Nasour Bagheri
2019 J jnl
A fully linear 5.2 GHz - 5.8 GHz digitally controlled oscillator in 65-nm CMOS technology.
Microelectron. J.
Siavash Heydarzadeh, Pooya Torkzadeh, Sirus Sadughi
2019 J jnl
A novel design of hybrid-time-interleaved current steering digital to analog converter and its behavioral simulation considering non-ideal effects.
Integr.
Hossein Sariri, Pooya Torkzadeh, Sirus Sadughi
2019 J jnl
A study of analog decision feedback equalization for ADC-Based serial link receivers.
Integr.
Azad Mahmoudi, Pooya Torkzadeh, Massoud Dousti
2019 J jnl
An accurate and power-efficient period-modulator-based interface for grounded capacitive sensors.
Int. J. Circuit Theory Appl.
Arash Ahmadpour Bijargah, Ali Heidary, Pooya Torkzadeh, Stoyan N. Nihtianov
2018 J jnl
Design trade-offs of a capacitance-to-voltage converter with a zoom-in technique for grounded capacitive sensors.
Int. J. Circuit Theory Appl.
Arash Ahmadpour Bijargah, Ali Heidary, Pooya Torkzadeh, Stoyan N. Nihtianov
2010 J jnl
Behavioral modeling of clock feed-through and channel charge injection non-ideal effects in SIMULINK for switched-capacitor integrator.
Simul. Model. Pract. Theory
Pooya Torkzadeh, Seyed Mojtaba Atarodi
2005 — conf
A fractional delay-locked loop for on chip clock generation applications.
ASP-DAC
Pooya Torkzadeh, Armin Tajalli, Seyed Mojtaba Atarodi
2005 — conf
A wide tuning range, 1 GHz-2.5 GHz DLL-based fractional frequency synthesizer.
ISCAS (5)
Pooya Torkzadeh, Armin Tajalli, Seyed Mojtaba Atarodi
2005 — conf
Analysis of jitter peaking and jitter accumulation in re-circulating delay-locked loops.
ISCAS (3)
Pooya Torkzadeh, Armin Tajalli, Seyed Mojtaba Atarodi