Ponnathpur R. Mukund

12 papers C 3Journal 5Unranked 4
YearRankTypeTitle / Venue / Authors
2011 J jnl
Analog IC Design in Ultra-Thin Oxide CMOS Technologies With Significant Direct Tunneling-Induced Gate Current.
IEEE Trans. Circuits Syst. I Regul. Pap.
Eric Bohannon, Clyde Washburn, Ponnathpur R. Mukund
2011 J jnl
Scaling the bulk-driven MOSFET into deca-nanometer bulk CMOS processes.
Microelectron. Reliab.
Christopher Urban, James E. Moon, Ponnathpur R. Mukund
2010 J jnl
Passive and Active Reduction Techniques for On-Chip High-Frequency Digital Power Supply Noise.
IEEE Trans. Very Large Scale Integr. Syst.
Eric Bohannon, Christopher Urban, Mark Pude, Yoshinori Nishi, Anand Gopalan, Ponnathpur R. Mukund
2006 C conf
A universal common-source and common-drain model for 1-20GHz frequency range.
ISCAS
S. Sridharan, Sripriya R. Bandi, Clyde Washburn, Ponnathpur R. Mukund, Jan Kolnik, Ken Paradis, Steve Howard, Jeff Burleson
2006 C conf
An analytical propagation delay model with power supply noise effects.
ISCAS
Mark Pude, Clyde Washburn, Ponnathpur R. Mukund, Kouichi Abe, Yoshinori Nishi
2006 C conf
Self-calibration of gain and output match in LNAs.
ISCAS
Tejasvi Das, Ponnathpur R. Mukund
2005 J jnl
1/f noise synthesis model in discrete-time for circuit simulation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Rajesh Narasimha, Sripriya R. Bandi, Raghuveer M. Rao, Ponnathpur R. Mukund
2005 J jnl
Self-calibration of input-match in RF front-end circuitry.
IEEE Trans. Circuits Syst. II Express Briefs
Tejasvi Das, Anand Gopalan, Clyde Washburn, Ponnathpur R. Mukund
2005 — conf
Use of source degeneration for non-intrusive BIST of RF front-end circuits.
ISCAS (5)
Anand Gopalan, Tejasvi Das, Clyde Washburn, Ponnathpur R. Mukund
2004 — conf
A compensation technique for transistor mismatch in current mirrors.
SoCC
Sripriya R. Bandi, Ponnathpur R. Mukund
2004 — conf
A generic macromodel for coupling between inductors and interconnects for R.F.I.C. layouts.
SoCC
Tejasvi Das, Ghanshyam Nayak, Ponnathpur R. Mukund
2002 — conf
Analysis of VCO jitter in chip-package co-design.
ISCAS (3)
H. Parthasarathy, Ghanshyam Nayak, Ponnathpur R. Mukund