Po-Yao Chuang

17 papers A* 1A 2B 4Misc 2Journal 2Unranked 6
YearRankTypeTitle / Venue / Authors
2025 — conf
Chiplet Interconnect Repair for Clustered Defects with Minimal Propagation Delay.
ATS
Po-Yao Chuang, Erik Jan Marinissen
2025 A conf
Chiplet Interconnect Test and Repair.
ITC
Po-Yao Chuang, Cheng-Wen Wu, Erik Jan Marinissen
2025 A conf
Chiplets' Die-to-Die Interconnect Repair Language (IRL).
ITC
Po-Yao Chuang, Erik Jan Marinissen
2025 B conf
Extendable E
ETS
Po-Yao Chuang, Erik Jan Marinissen
2025 J jnl
Generating Test Patterns for Chiplet Interconnects With Optimized Effectiveness and Efficiency.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Po-Yao Chuang, Francesco Lorenzelli, Cheng-Wen Wu, Erik Jan Marinissen
2024 Misc conf
IEEE Std P3405: New Standard-under-Development for Chiplet Interconnect Test and Repair.
VTS
Erik Jan Marinissen, Vineet Pancholi, Po-Yao Chuang, Martin Keim
2024 B conf
New Standard-under-Development for Chiplet Interconnect Test and Repair: IEEE Std P3405.
ETS
Erik Jan Marinissen, Adrian Evans, Po-Yao Chuang, Martin Keim, Anshuman Chandra
2024 B conf
Test and Repair Improvements for UCIe.
ETS
Tsung-Hsuan Wang, Po-Yao Chuang, Francesco Lorenzelli, Erik Jan Marinissen
2023 — conf
Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages.
3DIC
Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Slimane Boutobza, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen
2023 Misc conf
Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages.
VTS
Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen
2023 — conf
Generating Test Patterns for Chiplet Interconnects: Achieving Optimal Effectiveness and Efficiency.
ITC-Asia
Po-Yao Chuang, Francesco Lorenzelli, Erik Jan Marinissen
2022 — conf
A Thermal Quorum Sensing Scheme for Enhancement of Integrated-Circuit Reliability and Lifetime.
VLSI-DAT
Hong-Hao Wang, Po-Yao Chuang, Cheng-Wen Wu
2020 A* conf
A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object Classification.
DAC
Po-Yao Chuang, Pai-Yu Tan, Cheng-Wen Wu, Juin-Ming Lu
2020 J jnl
A Power-Efficient Binary-Weight Spiking Neural Network Architecture for Real-Time Object Classification.
CoRR
Pai-Yu Tan, Po-Yao Chuang, Yen-Ting Lin, Cheng-Wen Wu, Juin-Ming Lu
2018 B conf
Covering hard-to-detect defects by thermal quorum sensing.
ETS
Po-Yao Chuang, Cheng-Wen Wu, Harry H. Chen
2017 — conf
Cell-aware test generation time reduction by using switch-level ATPG.
ITC-Asia
Po-Yao Chuang, Cheng-Wen Wu, Harry H. Chen
2016 — conf
Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation.
ATS
Harry H. Chen, Simon Y.-H. Chen, Po-Yao Chuang, Cheng-Wen Wu