Po-Yang Hsu

11 papers A 2Journal 5Unranked 4
YearRankTypeTitle / Venue / Authors
2021 — conf
A 7nm 5G Mobile SoC Featuring a 3.0GHz Tri-Gear Application Processor Subsystem.
ISSCC
HsinChen Chen, Rolf Lagerquist, Ashish Nayak, Hugh Mair, Gokulakrishnan Manoharan, Ericbill Wang, Gordon Gammie, Efron Ho, Anand Rajagopalan, Lee-Kee Yong, Ramu Madhavaram, Madhur Jagota, Chi-Jui Chung, Sudhakar Maruthi, Jenny Wiedemeier, Tao Chen, Henry Hsieh, Daniel Dia, Amjad Sikiligiri, Manzur Rahman, Barry Chen, Curtis Lin, Vincent Lin, Elly Chiang, Cheng-Yuh Wu, Po-Yang Hsu, Jason Tsai, Wade Wu, Achuta Thippana, S. A. Huang
2015 J jnl
Reducing the Standby Power Consumption of the S3 State for PCs.
IEICE Trans. Electron.
Te Huang, Ying-Wen Bai, Po-Yang Hsu
2014 J jnl
Buffer Design and Assignment for Structured ASIC.
J. Inf. Sci. Eng.
Po-Yang Hsu, Yi-Yu Liu
2014 A conf
Compaction-free compressed cache for high performance multi-core system.
ICCAD
Po-Yang Hsu, Pei-Lan Lin, TingTing Hwang
2014 J jnl
Hybrid LUT and SOP Reconfigurable Architecture.
J. Inf. Sci. Eng.
Po-Yang Hsu, Yung-Chih Chen, Yi-Yu Liu
2014 J jnl
Stacking Signal TSV for Thermal Dissipation in Global Routing for 3-D IC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Po-Yang Hsu, Hsien-Te Chen, TingTing Hwang
2013 — conf
Reducing the standby power consumption of the S3 state for PCS.
CCECE
Te Huang, Ying-Wen Bai, Po-Yang Hsu
2013 J jnl
Routability optimization for crossbar-switch structured ASIC design.
ACM Trans. Design Autom. Electr. Syst.
Mei-Hsiang Tsai, Po-Yang Hsu, Hung-Yi Li, Yi-Huang Hung, Yi-Yu Liu
2013 — conf
Stacking signal TSV for thermal dissipation in global routing for 3D IC.
ASP-DAC
Po-Yang Hsu, Hsien-Te Chen, TingTing Hwang
2013 A conf
Thread-criticality aware dynamic cache reconfiguration in multi-core system.
ICCAD
Po-Yang Hsu, TingTing Hwang
2009 — conf
Buffer design and optimization for lut-based structured ASIC design styles.
ACM Great Lakes Symposium on VLSI
Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu