Po-Tsang Huang

79 papers B 1C 10Misc 3Journal 20Unranked 45
YearRankTypeTitle / Venue / Authors
2025 J jnl
An Energy-Area-Efficient 3D Interleaved-Ring Accelerator With INT/FP Pipelined PE Array and 3D-SRAM Cube for On-Device CNN Training and DM Inference.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wei Lu, Hung-Ming Chen, Po-Tsang Huang
2025 C conf
Irregular Operation-Unit-based Compression for Non-Volatile Computation-in-Memory Accelerator.
ISCAS
Liang-Te Huang, Wei Lu, Hung-Ming Chen, Po-Tsang Huang
2025 J jnl
Miniaturized and Cost-Effective Programmable 2.5D/3.5D Platforms Enabled by Scalable Embedded Active Bridge Chipset.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Wei Lu, Jie Zhang, Yi-Hui Wei, Hsu-Ming Hsiao, Sih-Han Li, Chao-Kai Hsu, Chih-Cheng Hsiao, Feng-Hsiang Lo, Shyh-Shyuan Sheu, Chin-Hung Wang, Ching-Iang Li, Yung-Sheng Chang, Ming-Ji Dai, Wei-Chung Lo, Shih-Chieh Chang, Hung-Ming Chen, Kuan-Neng Chen, Po-Tsang Huang
2024 — conf
3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25×33mm
VLSI Technology and Circuits
Bo-Jheng Shih, Yu-Ming Pan, Hao-Tung Chung, Chieh-Ling Lee, I-Chun Hsieh, Nein-Chih Lin, Chih-Chao Yang, Po-Tsang Huang, Hung-Ming Chen, Chiao-Yen Wang, Huan-Yu Chiu, Huang-Chung Cheng, Chang-Hong Shen, Wen-Fa Wu, Tuo-Hung Hou, Kuan-Neng Chen, Chenming Hu
2024 — conf
A 28nm 343.5fps/W Vision Transformer Accelerator with Integer-Only Quantized Attention Block.
AICAS
Cheng-Chen Lin, Wei Lu, Po-Tsang Huang, Hung-Ming Chen
2024 C conf
A 28nm Energy-Area-Efficient Row-based pipelined Training Accelerator with Mixed FXP4/FP16 for On-Device Transfer Learning.
ISCAS
Wei Lu, Han-Hsiang Pei, Jheng-Rong Yu, Hung-Ming Chen, Po-Tsang Huang
2024 — conf
Design Exploration of In-Situ Error Correction for Multi-Bit Computation-in-Memory Circuits.
APCCAS
Ting-An Lin, Po-Tsang Huang
2024 J jnl
Energy-Efficient Sparse FFT and Compressed Transpose Memory for mmWave FMCW Radar Sensor System.
IEEE Trans. Instrum. Meas.
Tourangbam Harishore Singh, Po-Tsang Huang, Kung-Shuo Kao, Chih-Shiang Cheng, Kuei-Ann Wen, Lichun Wang
2024 — conf
Scalable Embedded Multi-Die Active Bridge (S-EMAB) Chips with Integrated LDOs for Low-Cost Programmable 2.5D/3.5D Packaging Technology.
VLSI Technology and Circuits
Wei Lu, Jie Zhang, Yi-Hui Wei, Hsu-Ming Hsiao, Sih-Han Li, Chao-Kai Hsu, Chih-Cheng Hsiao, Feng-Hsiang Lo, Shyh-Shyuan Sheu, Chin-Hung Wang, Wei-Chung Lo, Shih-Chieh Chang, Hung-Ming Chen, Kuan-Neng Chen, Po-Tsang Huang
2023 — conf
On-Interposer Decoupling Capacitors Placement for Interposer-based 3DIC.
ISQED
Po-Yang Chen, Chang-Yun Liu, Hung-Ming Chen, Po-Tsang Huang
2023 — conf
Reshaping System Design in 3D Integration: Perspectives and Challenges.
ISPD
Hung-Ming Chen, Chu-Wen Ho, Shih-Hsien Wu, Wei Lu, Po-Tsang Huang, Hao-Ju Chang, Chien-Nan Jimmy Liu
2022 — conf
An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology.
VLSI Technology and Circuits
Jie Zhang, Wei Lu, Po-Tsang Huang, Sih-Han Li, Tsung-Yi Hung, Shih-Hsien Wu, Ming-Ji Dai, I-Shan Chung, Wen-Chao Chen, Chin-Hung Wang, Shyh-Shyuan Sheu, Hung-Ming Chen, Kuan-Neng Chen, Wei-Chung Lo, Chih-I Wu
2022 — conf
Cognitive Bus Coding Scheme for Inter-Chip Communications of Deep Learning Accelerator Chiplet on Low-cost Si and Glass Interposer.
MCSoC
Yu-Hong Chang, Tourangbam Harishore Singh, Po-Tsang Huang
2022 — conf
Design Exploration of An Energy-Efficient Acceleration System for CNNs on Low-Cost Resource-Constraint SoC-FPGAs.
AICAS
Shao-Cheng Wen, Po-Tsang Huang
2022 J jnl
Digi-FH-OFDM: An all-digital wideband frequency-hopped OFDM system.
Phys. Commun.
Amit Sravan Bora, Tourangbam Harishore Singh, Po-Tsang Huang
2022 — conf
Digital Computation-in-Memory Design with Adaptive Floating Point for Deep Neural Networks.
MCSoC
Yun-Ru Yang, Wei Lu, Po-Tsang Huang, Hung-Ming Chen
2022 — conf
Interfacial Layer Engineering to Enhance Noise Immunity of FeFETs for IMC Applications.
ICICDT
Yannick Raffel, Sunanda Thunder, Maximilian Lederer, Ricardo Olivo, Raik Hoffmann, Luca Pirro, Sven Beyer, Talha Chohan, Po-Tsang Huang, Sourav De, Thomas Kämpfe, Konrad Seidel, Johannes Heitmann
2022 — conf
Memory-Centric Fusion-based CNN Accelerator with 3D-NoC and 3D-DRAM.
ISOCC
Wei Lu, Pei-Yu Ge, Po-Tsang Huang, Hung-Ming Chen, Wei Hwang
2022 — conf
Precision-Aware Workload Distribution and Dataflow for a Hybrid Digital-CIM Deep CNN Accelerator.
ISOCC
Jui-I Kao, Wei Lu, Po-Tsang Huang, Hung-Ming Chen
2022 J jnl
Variation Aware Training of Hybrid Precision Neural Networks with 28nm HKMG FeFET Based Synaptic Core.
CoRR
Sunanda Thunder, Po-Tsang Huang
2021 J jnl
An Energy-Efficient 3D Cross-Ring Accelerator With 3D-SRAM Cubes for Hybrid Deep Neural Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Wei Lu, Po-Tsang Huang, Hung-Ming Chen, Wei Hwang
2021 — conf
An Energy-Efficient Ring-Based CIM Accelerator using High-Linearity eNVM for Deep Neural Networks.
ISOCC
Po-Tsang Huang, Ting-Wei Liu, Wei Lu, Yu-Hsien Lin, Wei Hwang
2021 J jnl
Design and Implementation for Deep Learning Based Adjustable Beamforming Training for Millimeter Wave Communication Systems.
IEEE Trans. Veh. Technol.
Li-Hsiang Shen, Ting-Wei Chang, Kai-Ten Feng, Po-Tsang Huang
2021 J jnl
Energy-Efficient Accelerator Design With Tile-Based Row-Independent Compressed Memory for Sparse Compressed Convolutional Neural Networks.
IEEE Open J. Circuits Syst.
Po-Tsang Huang, I-Chen Wu, Chin-Yang Lo, Wei Hwang
2021 J jnl
Rotational motion-aware beam refinement for high-throughput mmWave communications.
Wirel. Networks
Tourangbam Harishore Singh, Shabirahmed Badashasab Jigalur, Po-Tsang Huang
2021 — conf
Ultra Low Power 3D-Embedded Convolutional Neural Network Cube Based on α-IGZO Nanosheet and Bi-Layer Resistive Memory.
ICICDT
Sunanda Thunder, Parthasarathi Pal, Yeong-Her Wang, Po-Tsang Huang
2021 J jnl
Ultra Low Power 3D-Embedded Convolutional Neural Network Cube Based on α-IGZO Nanosheet and Bi-Layer Resistive Memory.
CoRR
Sunanda Thunder, Parthasarathi Pal, Yeong-Her Wang, Po-Tsang Huang
2020 J jnl
3D On-Demand Flying Mobile Communication for Millimeter-Wave Heterogeneous Networks.
IEEE Netw.
Kai-Ten Feng, Li-Hsiang Shen, Chi-Yu Li, Po-Tsang Huang, Sau-Hsuan Wu, Li-Chun Wang, Yi-Bing Lin, Mau-Chung Frank Chang
2020 — conf
Energy-Efficient Accelerator Design with 3D-SRAM and Hierarchical Interconnection Architecture for Compact Sparse CNNs.
AICAS
Chin-Yang Lo, Po-Tsang Huang, Wei Hwang
2020 — conf
Hierarchical Active Voltage Regulation for Heterogeneous TSV 3D-ICs.
SoCC
Po-Tsang Huang, Tzung-Han Tsai, Po-Jen Yang, Wei Hwang, Hung-Ming Chen
2019 — conf
28nm 0.3V 1W2R Sub-Threshold FIFO Memory for Multi-Sensor IoT Applications.
SoCC
Huan-Jan Tseng, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang
2019 — conf
A 7.5-mW 10-Gb/s 16-QAM wireline transceiver with carrier synchronization and threshold calibration for mobile inter-chip communications in 16-nm FinFET.
NOCS
Jieqiong Du, Chien-Heng Wong, Yo-Hao Tu, Wei-Han Cho, Yilei Li, Yuan Du, Po-Tsang Huang, Sheau Jiung Lee, Mau-Chung Frank Chang
2019 — conf
An Energy-Efficient Accelerator with Relative- Indexing Memory for Sparse Compressed Convolutional Neural Network.
AICAS
I-Chen Wu, Po-Tsang Huang, Chin-Yang Lo, Wei Hwang
2019 J jnl
Built-In Self-Test/Repair Methodology for Multiband RF-Interconnected TSV 3D Integration.
IEEE Des. Test
Shu-Feng Cheng, Po-Tsang Huang, Li-Chun Wang, Mau-Chung Frank Chang
2018 — conf
0.4V Reconfigurable Near-Threshold TCAM in 28nm High-k Metal-Gate CMOS Process.
SoCC
Yun-Sheng Chan, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang
2018 — conf
28nm near/sub-threshold dual-port FIFO memory for shared queues in multi-sensor applications.
VLSI-DAT
Yi-Chun Wu, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang
2018 Misc conf
SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for DNA Sequencing.
FCCM
Jason Cong, Licheng Guo, Po-Tsang Huang, Peng Wei, Tianhe Yu
2018 B conf
SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for Genome Sequencing.
FPL
Jason Cong, Licheng Guo, Po-Tsang Huang, Peng Wei, Tianhe Yu
2017 J jnl
A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shang-Lin Wu, Kuang-Yu Li, Po-Tsang Huang, Wei Hwang, Ming-Hsien Tu, Sheng-Chi Lung, Wei-Sheng Peng, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao, Ching-Te Chuang
2017 J jnl
A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection.
IEEE J. Solid State Circuits
Yuan Du, Wei-Han Cho, Po-Tsang Huang, Yilei Li, Chien-Heng Wong, Jieqiong Du, Yanghyo Kim, Boyu Hu, Li Du, Chun-Chen Liu, Sheau Jiung Lee, Mau-Chung Frank Chang
2017 C conf
An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer.
ISCAS
Po-Tsang Huang, Yu-Chieh Huang, Shang-Lin Wu, Yu-Chen Hu, Ming-Wei Lu, Ting-Wei Sheng, Fung-Kai Chang, Chun-Pin Lin, Nien-Shang Chang, Hung-Lieh Chen, Chi-Shi Chen, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou
2017 C conf
Exploration and evaluation of low-dropout linear voltage regulator with FinFET, TFET and hybrid TFET-FinFET implementations.
ISCAS
Chia-Ning Chang, Yin-Nien Chen, Po-Tsang Huang, Pin Su, Ching-Te Chuang
2017 J jnl
Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes.
IEEE Trans. Biomed. Circuits Syst.
Yu-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Yu-Chen Hu, Yan-Huei You, Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou
2016 — conf
10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface.
ISSCC
Wei-Han Cho, Yilei Li, Yuan Du, Chien-Heng Wong, Jieqiong Du, Po-Tsang Huang, Sheau Jiung Lee, Huan-Neng Ron Chen, Chewnpu Jou, Fu-Lung Hsueh, Mau-Chung Frank Chang
2016 — conf
A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS.
VLSI Circuits
Yuan Du, Wei-Han Cho, Yilei Li, Chien-Heng Wong, Jieqiong Du, Po-Tsang Huang, Yanghyo Kim, Zuow-Zun Chen, Sheau Jiung Lee, Mau-Chung Frank Chang
2016 C conf
An ultra-high-density 256-channel/25mm2 neural sensing microsystem using TSV-embedded neural probes.
ISCAS
Yu-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Yu-Chen Hu, Yan-Huei You, Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou
2016 — conf
Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application.
SoCC
Ming Chen, Po-Tsang Huang, Shang-Lin Wu, Wei Hwang, Ching-Te Chuang
2016 Misc conf
The SMEM Seeding Acceleration for DNA Sequence Alignment.
FCCM
Mau-Chung Frank Chang, Yu-Ting Chen, Jason Cong, Po-Tsang Huang, Chun-Liang Kuo, Cody Hao Yu
2015 — conf
A 5.4-mW 4-Gb/s 5-band QPSK transceiver for frequency-division multiplexing memory interface.
CICC
Wei-Han Cho, Yilei Li, Yanghyo Kim, Po-Tsang Huang, Yuan Du, Sheau Jiung Lee, Mau-Chung Frank Chang
2015 — conf
All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction.
VLSI-DAT
Yi-Ping Kuo, Po-Tsang Huang, Chung-Shiang Wu, Yu-Jie Liang, Ching-Te Chuang, Yuan-Hua Chu, Wei Hwang
2015 — conf
Energy-efficient gas recognition system with event-driven power control.
SoCC
Chun-Ying Huang, Po-Tsang Huang, Chih-Chao Yang, Ching-Te Chuang, Wei Hwang
2015 — conf
Low power algorithm-architecture co-design of fast Independent Component Analysis (FICA) for multi-gas sensor applications.
VLSI-DAT
Chih-Chao Yang, Po-Tsang Huang, Chun-Ying Huang, Ching-Te Chuang, Wei Hwang
2014 — conf
0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOS.
A-SSCC
Po-Tsang Huang, Shu-Lin Lai, Ching-Te Chuang, Wei Hwang, Jason Huang, Angelo Hu, Paul Kan, Michael Jia, Kimi Lv, Bright Zhang
2014 — conf
18.6 2.5D heterogeneously integrated bio-sensing microsystem for multi-channel neural-sensing applications.
ISSCC
Po-Tsang Huang, Lei-Chun Chou, Teng-Chieh Huang, Shang-Lin Wu, Tang-Shuan Wang, Yu-Rou Lin, Chuan-An Cheng, Wen-Wei Shen, Kuan-Neng Chen, Jin-Chern Chiou, Ching-Te Chuang, Wei Hwang, Kuo-Hua Chen, Chi-Tsung Chiu, Ming-Hsiang Cheng, Yueh-lung Lin, Ho-Ming Tong
2014 J jnl
2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications.
IEEE Trans. Biomed. Circuits Syst.
Po-Tsang Huang, Shang-Lin Wu, Yu-Chieh Huang, Lei-Chun Chou, Teng-Chieh Huang, Tang-Hsuan Wang, Yu-Rou Lin, Chuan-An Cheng, Wen-Wei Shen, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Ho-Ming Tong
2014 C conf
Energy-efficient configurable discrete wavelet transform for neural sensing applications.
ISCAS
Tang-Hsuan Wang, Po-Tsang Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang
2014 — conf
Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition.
VLSI-DAT
Shang-Lin Wu, Po-Tsang Huang, Teng-Chieh Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang
2014 — conf
Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video.
SoCC
Chih-Yuan Chang, Po-Tsang Huang, Yi-Chun Chen, Tian-Sheuan Chang, Wei Hwang
2013 — conf
Area-power-efficient 11-bit SAR ADC with delay-line enhanced tuning for neural sensing applications.
BioCAS
Teng-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang
2013 — conf
Through-silicon-via-based double-side integrated microsystem for neural sensing applications.
ISSCC
Chih-Wei Chang, Po-Tsang Huang, Lei-Chun Chou, Shang-Lin Wu, Shih-Wei Lee, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Yen-Chi Lee, Chung-Hsi Wu, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong
2012 — conf
A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs.
VLSI-DAT
Wei-Hung Du, Po-Tsang Huang, Ming-Hung Chang, Wei Hwang
2012 — conf
On-chip self-calibrated process-temperature sensor for TSV 3D integration.
SoCC
Tzu-Ting Chiang, Po-Tsang Huang, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Wei Hwang
2012 J jnl
Self-Calibrated Energy-Efficient and Reliable Channels for On-Chip Interconnection Networks.
J. Electr. Comput. Eng.
Po-Tsang Huang, Wei Hwang
2012 C conf
Substrate noise suppression technique for power integrity of TSV 3D integration.
ISCAS
Po-Jen Yang, Po-Tsang Huang, Wei Hwang
2011 J jnl
A 65 nm 0.165 fJ/Bit/Search 256 , ˟, 144 TCAM Macro Design for IPv6 Lookup Tables.
IEEE J. Solid State Circuits
Po-Tsang Huang, Wei Hwang
2011 — conf
On-demand memory sub-system for multi-core SoCs.
SoCC
Po-Tsang Huang, Yung Chang, Wei Hwang
2011 J jnl
Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Po-Tsang Huang, Wei Hwang
2010 J jnl
A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder.
J. Low Power Electron.
Po-Tsang Huang, Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee, Wei Hwang
2010 Misc conf
A decision support system of statistical process control for printed circuit boards manufacturing.
ICMLC
Hsin Rau, Chien-Hung Wu, Wei-Jung Shiang, Po-Tsang Huang
2010 — conf
Power noise suppression technique using active decoupling capacitor for TSV 3D integration.
SoCC
Tien-Hung Lin, Po-Tsang Huang, Wei Hwang
2009 — conf
An adaptive congestion-aware routing algorithm for mesh network-on-chip platform.
SoCC
Po-Tsang Huang, Wei Hwang
2008 C conf
"Green" micro-architecture and circuit co-design for ternary content addressable memory.
ISCAS
Po-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu, Wei Hwang
2008 C conf
A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop.
ISCAS
Li-Pu Chuang, Ming-Hung Chang, Po-Tsang Huang, Chih-Hao Kan, Wei Hwang
2008 — conf
A robust ultra-low power asynchronous FIFO memory with self-adaptive power control.
SoCC
Mu-Tien Chang, Po-Tsang Huang, Wei Hwang
2008 — conf
Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip.
NOCS
Po-Tsang Huang, Wei-Li Fang, Yin-Ling Wang, Wei Hwang
2007 — conf
A 65nm low power 2T1D embedded DRAM with leakage current reduction.
SoCC
Mu-Tien Chang, Po-Tsang Huang, Wei Hwang
2006 C conf
2-level FIFO architecture design for switch fabrics in network-on-chip.
ISCAS
Po-Tsang Huang, Wei Hwang
2006 — conf
Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory.
APCCAS
Po-Tsang Huang, Wei-Keng Chang, Wei Hwang
2006 — conf
On-Chip DC-DC Converter with Frequency Detector for Dynamic Voltage Scaling Technology.
APCCAS
Jen-Wei Yang, Po-Tsang Huang, Wei Hwang