| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2024 | — | conf |
GCCE
|
| 2020 | J | jnl |
IEEE Trans. Emerg. Top. Comput.
|
| 2019 | J | jnl |
New Rev. Hypermedia Multim.
|
| 2017 | — | conf |
MMLA-CrossLAK@LAK
|
| 2017 | A | conf |
LAK
|
| 2017 | B | conf |
EDM
|
| 2016 | J | jnl |
IEEE J. Solid State Circuits
|
| 2015 | — | conf |
ISSCC
|
| 2015 | J | jnl |
IEEE/ACM Trans. Netw.
|
| 2013 | J | jnl |
IEEE/ACM Trans. Netw.
|
| 2013 | B | conf |
SECON
|
| 2013 | — | conf |
Allerton
|
| 2013 | A* | conf |
INFOCOM
|
| 2013 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2012 | A | conf |
Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction.
DATE
|
| 2011 | A* | conf |
INFOCOM
|
| 2011 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2011 | A* | conf |
DAC
|
| 2010 | — | conf |
Allerton
|
| 2007 | J | jnl |
IEEE Trans. Ind. Electron.
|
| 2007 | J | jnl |
IEEE Trans. Inf. Theory
|
| 2006 | J | jnl |
IEEE Trans. Ind. Electron.
|
| 2006 | J | jnl |
IEEE Trans. Neural Networks
|
| 2006 | J | jnl |
SIGMETRICS Perform. Evaluation Rev.
|