Po-Chiun Huang

51 papers A* 1B 1C 3Journal 24Unranked 22
YearRankTypeTitle / Venue / Authors
2024 — conf
A CMOS Transimpedance Amplifier Accommodating Wide CPD and Input Bias Range for Chaos Lidar.
APCCAS
Hao-Wei Wu, Chung-Yuan Wang, Huan-Jhong Chen, Yi-Cheng Lin, Ping-Hsuan Hsieh, Fan-Yi Lin, Yuan-Hao Huang, Po-Chiun Huang
2022 J jnl
Guest Editorial Introduction to the Special Section on the 2021 Asian Solid-State Circuits Conference (A-SSCC).
IEEE J. Solid State Circuits
Jung-Hwan Choi, Po-Chiun Huang, Shouyi Yin, Woogeun Rhee
2021 — conf
A Cross-Correlation-Based Time-of-Flight Design for Chaos Lidar Systems.
A-SSCC
Yi-Cheng Lin, Ping-Hsuan Hsieh, Jian-Lun Hong, Yu-Hsiang Lai, Jun-Da Chen, Fan-Yi Lin, Yuan-Hao Huang, Po-Chiun Huang
2020 — conf
2 x 3 Arrayed CMOS Capacitive Biosensors for Detection of microRNAs on a Microfluidic System.
NEMS
Yu-Husan Kuo, Chi-Chien Huang, Yi-Sin Chen, Po-Chiun Huang, Gwo-Bin Lee
2020 J jnl
Portable Sleep Apnea Syndrome Screening and Event Detection Using Long Short-Term Memory Recurrent Neural Network.
Sensors
Hung-Chi Chang, Hau-Tieng Wu, Po-Chiun Huang, Hsi-Pin Ma, Yu-Lun Lo, Yuan-Hao Huang
2018 C conf
A Portable Monitoring System with Automatic Event Detection for Sleep Apnea Level-IV Evaluation.
ISCAS
Jhao-Cheng Wu, Chia-Wei Wang, Yuan-Hao Huang, Hau-Tieng Wu, Po-Chiun Huang, Yu-Lun Lo
2018 J jnl
Electromagnetic Energy Harvester Interface Design for Wearable Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Shih-Wei Wang, Yi-Wen Ke, Po-Chiun Huang, Ping-Hsuan Hsieh
2017 J jnl
Sleep Apnea Detection Based on Thoracic and Abdominal Movement Signals of Wearable Piezoelectric Bands.
IEEE J. Biomed. Health Informatics
Yin-Yan Lin, Hau-Tieng Wu, Chi-An Hsu, Po-Chiun Huang, Yuan-Hao Huang, Yu-Lun Lo
2016 J jnl
A Battery-Less, Implantable Neuro-Electronic Interface for Studying the Mechanisms of Deep Brain Stimulation in Rat Models.
IEEE Trans. Biomed. Circuits Syst.
Yu-Po Lin, Chun-Yi Yeh, Pin-Yang Huang, Zong-Ye Wang, Hsiang-Hui Cheng, Yi-Ting Li, Chi-Fen Chuang, Po-Chiun Huang, Kea-Tiong Tang, Hsi-Pin Ma, Yen-Chung Chang, Shih-Rung Yeh, Hsin Chen
2016 J jnl
Cooperation between Distributed Power Modules for SoC Power Management.
IEICE Trans. Electron.
Po-Chiun Huang, Shin-Jie Huang, Po-Hsiang Lan
2015 J jnl
A 0.003 mm
IEEE J. Solid State Circuits
Jen-Huan Tsai, Hui-Huan Wang, Yang-Chi Yen, Chang-Ming Lai, Yen-Ju Chen, Po-Chiun Huang, Ping-Hsuan Hsieh, Hsin Chen, Chao-Cheng Lee
2015 J jnl
A 1 V Input, 3 V-to-6 V Output, 58%-Efficient Integrated Charge Pump With a Hybrid Topology for Area Reduction and an Improved Efficiency by Using Parasitics.
IEEE J. Solid State Circuits
Jen-Huan Tsai, Sheng-An Ko, Chia-Wei Wang, Yang-Chi Yen, Hui-Huan Wang, Po-Chiun Huang, Po-Hsiang Lan, Meng-Hung Shen
2015 J jnl
A Wide-Range Multiport LC-Ladder Oscillator and Its Applications to a 1.2-10.1 GHz PLL.
IEEE Trans. Very Large Scale Integr. Syst.
Meng-Hung Shen, Po-Chiun Huang
2014 — conf
28.3 A frequency-defined vernier digital-to-time converter for impulse radar systems in 65nm CMOS.
ISSCC
Yu-Hsien Kao, Chang-Ming Lai, Jen-Ming Wu, Po-Chiun Huang, Ping-Hsuan Hsieh, Ta-Shun Chu
2014 J jnl
A 1-V-0.6-V 9-b 1.5-MS/s Reference-Free Charge-Sharing SAR ADC for Wireless-Powered Implantable Telemetry.
IEEE Trans. Circuits Syst. II Express Briefs
Jen-Huan Tsai, Hui-Huan Wang, Yen-Ju Chen, Yen-Hsin Wei, Yo-Hsien Kao, Yang-Chi Yen, Po-Chiun Huang, Meng-Hung Shen, Hsin Chen
2014 — conf
A 1V input, 3-to-6V output, integrated 58%-efficient charge-pump with hybrid topology and parasitic energy collection for 66% area reduction and 11% efficiency improvement.
A-SSCC
Jen-Huan Tsai, Sheng-An Ko, Hui-Huan Wang, Chia-Wei Wang, Hsin Chen, Po-Chiun Huang
2014 — conf
A feedforward noise and distortion cancellation technique for CMOS broadband LNA-mixer.
A-SSCC
Chin-Fu Li, Shih-Chieh Chou, Chang-Ming Lai, Cuei-Ling Hsieh, Jenny Yi-Chun Liu, Po-Chiun Huang
2014 — conf
A mixed-signal phase-domain FSK demodulator for BLE single-path low-IF receiver.
VLSI-DAT
Cuei-Ling Hsieh, Chang-Ming Lai, Guan-Hong Ke, Jenny Yi-Chun Liu, Po-Chiun Huang
2014 — conf
An intelligent brain machine interface with wireless micro-stimulation and neural recording.
BHI
Hung-Chih Chiu, Yi-Ting Lee, Chi-Fen Chuang, Yen-Chung Chang, Shih-Rung Yeh, Po-Chiun Huang, Hsi-Pin Ma
2013 J jnl
A High-Efficiency, Wide Workload Range, Digital Off-Time Modulation (DOTM) DC-DC Converter With Asynchronous Power Saving Technique.
IEEE Trans. Very Large Scale Integr. Syst.
Po-Hsiang Lan, Tsung-Ju Yang, Po-Chiun Huang
2013 — conf
A scalable direct-sampling broadband radar receiver supporting simultaneous digital multibeam array in 65nm CMOS.
ISSCC
Chang-Ming Lai, Jen-Ming Wu, Po-Chiun Huang, Ta-Shun Chu
2013 J jnl
AC-Plus Scan Methodology for Small Delay Testing and Characterization.
IEEE Trans. Very Large Scale Integr. Syst.
Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Ching-Cheng Tien, Chi-Hu Wang, Cheng-Wen Wu
2013 — conf
An implantable microsystem for long-term study on the mechanism of deep brain stimulation.
BioCAS
Yu-Po Lin, Hung-Chih Chiu, Pin-Yang Huang, Zong-Ye Wang, Hsiang-Hui Cheng, Po-Chiun Huang, Kea-Tiong Tang, Hsi-Pin Ma, Hsin Chen
2013 — conf
Time-domain analog-to-digital converters with domino delay lines.
VLSI-DAT
Chang-Ming Lai, Yi-Chung Chen, Po-Chiun Huang
2012 — conf
A 14-bit 200MS/s current-steering DAC achieving over 82dB SFDR with digitally-assisted calibration and dynamic matching techniques.
VLSI-DAT
Jen-Huan Tsai, Yen-Ju Chen, Yan-Fong Lai, Meng-Hung Shen, Po-Chiun Huang
2012 J jnl
A High Efficiency FLL-Assisted Current-Controlled DC-DC Converter Over Light-Loaded Range.
IEEE Trans. Circuits Syst. I Regul. Pap.
Po-Hsiang Lan, Po-Chiun Huang
2012 J jnl
A Low Cost Calibrated DAC for High-Resolution Video Display System.
IEEE Trans. Very Large Scale Integr. Syst.
Meng-Hung Shen, Po-Chiun Huang
2012 J jnl
A Power-Efficient Noise Suppression Technique Using Signal-Nulled Feedback for Low-Noise Wideband Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs
Chin-Fu Li, Shih-Chieh Chou, Guan-Hong Ke, Po-Chiun Huang
2012 — conf
A UWB IR timed-array radar using time-shifted direct-sampling architecture.
VLSIC
Chang-Ming Lai, Kai-Wen Tan, Liu-Yuan Yu, Yen-Ju Chen, Jun-Wei Huang, Shr-Chau Lai, Feng-Hsu Chung, Chia-Fung Yen, Jen-Ming Wu, Po-Chiun Huang, Keh-Jeng Chang, Shi-Yu Huang, Ta-Shun Chu
2012 — conf
An area-efficient CMOS switching converter with on-chip LC filter using feedforward ripple cancellation technique.
VLSI-DAT
Po-Hsiang Lan, Yao-Jun Kuo, Po-Chiun Huang
2012 — conf
An implantable microsystem for studying the Parkinson's Disease.
APCCAS
Yung-Chan Chen, Yu-Po Lin, Tsui-Ling Hsieh, Chun-Yi Yeh, Pin-Yang Huang, Hung-Chih Chiu, Zong-Ye Wang, Wen-Yang Hsu, Po-Chiun Huang, Kea-Tiong Tang, Hsi-Pin Ma, Hsin Chen
2011 C conf
A 0.24 to 2.4 GHz phase-locked loop with low supply sensitivity in 0.18-µm CMOS.
ISCAS
Chang-Ming Lai, Meng-Hung Shen, Yi-Da Wu, Kai-Hsiang Huang, Po-Chiun Huang
2011 — conf
A 90nm CMOS, 5.6ps, 0.23pJ/code time-to-digital converter with multipath oscillator and seamless cycle detection.
A-SSCC
Chang-Ming Lai, Meng-Hung Shen, Geng-Yi Pan, Po-Chiun Huang
2011 A* conf
A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing.
DAC
Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang
2011 — conf
A low-power CMOS LNA using noise suppression and distortion cancellation techniques with inductive bandwidth extension.
ISOCC
Chin-Fu Li, Chang-Ming Lai, Ping-Chuan Chiang, Po-Chiun Huang
2011 — conf
An asynchronous digitally-controlled switching converter with adaptive resolution and dynamic power saving to achieve higher than 93.5% efficiency between 5mA and 250mA load.
A-SSCC
Po-Hsiang Lan, Tsung-Ju Yang, Po-Chiun Huang
2010 J jnl
A Quantization Error Minimization Method Using DDS-DAC for Wideband Fractional-N Frequency Synthesizer.
IEEE J. Solid State Circuits
Yi-Da Wu, Chang-Ming Lai, Chao-Cheng Lee, Po-Chiun Huang
2010 — conf
AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects.
DFT
Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Mike Wang
2010 J jnl
An Integrated Linear Regulator With Fast Output Voltage Transition for Dual-Supply SRAMs in DVFS Systems.
IEEE J. Solid State Circuits
Chun-Yen Tseng, Li-Wen Wang, Po-Chiun Huang
2010 — conf
Design of a process-insensitive digital controller for high-frequency DC-DC SMPS.
APCCAS
Po-Hsiang Lan, Chun-Yen Tseng, Po-Chiun Huang
2010 J jnl
Random Swapping Dynamic Element Matching Technique for Glitch Energy Minimization in Current-Steering DAC.
IEEE Trans. Circuits Syst. II Express Briefs
Meng-Hung Shen, Jen-Huan Tsai, Po-Chiun Huang
2008 J jnl
A 1-V CMOS Pseudo-Differential Amplifier With Multiple Common-Mode Stabilization and Frequency Compensation Loops.
IEEE Trans. Circuits Syst. II Express Briefs
Meng-Hung Shen, Po-Hsiang Lan, Po-Chiun Huang
2007 — conf
A 1.2-V CMOS Limiter / RSSI / Demodulator for Low-IF FSK Receiver.
CICC
Yi-Chung Chen, Yi-Chang Wu, Po-Chiun Huang
2006 J jnl
A Low-Power CMOS Linear-in-Decibel Variable Gain Amplifier With Programmable Bandwidth and Stable Group Delay.
IEEE Trans. Circuits Syst. II Express Briefs
Shan-Chih Tsou, Chin-Fu Li, Po-Chiun Huang
2006 C conf
An OPLL-DDS based frequency synthesizer for DCS-1800 receiver.
ISCAS
Yi-Da Wu, Chang-Ming Lai, Chih-Yuan Chou, Po-Chiun Huang
2006 J jnl
Joint Polynomial and Look-Up-Table Predistortion Power Amplifier Linearization.
IEEE Trans. Circuits Syst. II Express Briefs
Hsin-Hung Chen, Chih-Hung Lin, Po-Chiun Huang, Jiunn-Tsair Chen
2005 — conf
Low-power techniques for network security processors.
ASP-DAC
Yi-Ping You, Chun-Yen Tseng, Yu-Hui Huang, Po-Chiun Huang, TingTing Hwang, Sheng-Yu Hsu
2004 B conf
Adaptive I/Q imbalance compensation for RF transceivers.
GLOBECOM
Hsin-Hung Chen, Jiunn-Tsair Chen, Po-Chiun Huang
2001 J jnl
A 2-V CMOS 455-kHz FM/FSK demodulator using feedforward offset cancellation limiting amplifier.
IEEE J. Solid State Circuits
Po-Chiun Huang, Yi-Huei Chen, Chorng-Kuang Wang
2000 J jnl
A 2-V 10.7-MHz CMOS limiting amplifier/RSSI.
IEEE J. Solid State Circuits
Po-Chiun Huang, Yi-Huei Chen, Chorng-Kuang Wang
1996 J jnl
A BiCMOS limiting amplifier for SONET OC-3.
IEEE J. Solid State Circuits
Chorng-Kuang Wang, Po-Chiun Huang, Chen-Yi Huang