Po-Chih Tseng

22 papers A 1C 1Journal 9Unranked 11
YearRankTypeTitle / Venue / Authors
2009 J jnl
Multimode Embedded Compression Codec Engine for Power-Aware Video Coding System.
IEEE Trans. Circuits Syst. Video Technol.
Chih-Chi Cheng, Po-Chih Tseng, Liang-Gee Chen
2007 — conf
Reconfigurable architecture for video applications.
SoCC
Chung-Jr Lian, Po-Chih Tseng, Tung-Chien Chen, Yu-Wei Chang, Liang-Gee Chen
2006 — conf
A 5mW MPEG4 SP encoder with 2D bandwidth-sharing motion estimation for mobile applications.
ISSCC
Chia-Ping Lin, Po-Chih Tseng, Yao-Ting Chiu, Siou-Shen Lin, Chih-Chi Cheng, Hung-Chi Fang, Wei-Min Chao, Liang-Gee Chen
2005 J jnl
Advances in Hardware Architectures for Image and Video Coding - A Survey.
Proc. IEEE
Po-Chih Tseng, Yung-Chi Chang, Yu-Wen Huang, Hung-Chi Fang, Chao-Tsung Huang, Liang-Gee Chen
2005 J jnl
Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform.
IEEE Trans. Signal Process.
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2005 J jnl
Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method.
IEEE Trans. Circuits Syst. Video Technol.
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2005 — conf
Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT.
ISCAS (5)
Chih-Chi Cheng, Chao-Tsung Huang, Po-Chih Tseng, Chia-Ho Pan, Liang-Gee Chen
2005 A conf
Nearly Lossless Content-Dependent Low-Power DCT Design for Mobile Video Applications.
ICME
Chia-Ping Lin, Po-Chih Tseng, Liang-Gee Chen
2005 J jnl
Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems.
J. VLSI Signal Process.
Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen
2005 J jnl
VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization.
J. VLSI Signal Process.
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2005 J jnl
VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters.
J. VLSI Signal Process.
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2004 — conf
B-spline factorization-based architecture for inverse discrete wavelet transform.
ISCAS (2)
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2004 J jnl
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform.
IEEE Trans. Signal Process.
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2004 — conf
Low-power parallel tree architecture for full search block-matching motion estimation.
ISCAS (2)
Siou-Shen Lin, Po-Chih Tseng, Liang-Gee Chen
2004 — conf
Memory analysis and architecture for two-dimensional discrete wavelet transform.
ICASSP (5)
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2004 — conf
Reconfigurable discrete cosine transform processor for object-based video signal processing.
ISCAS (2)
Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen
2003 — conf
Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9, 7) filter bank.
ICIP (2)
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2002 — conf
Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method.
ISCAS (5)
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2002 — conf
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform.
APCCAS (1)
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2002 — conf
Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method.
APCCAS (1)
Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen
2002 C conf
VLSI implementation of shape-adaptive discrete wavelet transform.
VCIP
Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen
2001 J jnl
CDSP: an application-specific digital signal processor for third generation wireless communications.
IEEE Trans. Consumer Electron.
Po-Chih Tseng, Chi-Kuang Chen, Liang-Gee Chen