Piotr Dudek - RankMe

100 papers A* 5A 4B 8C 27Journal 28Unranked 28

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A General-Purpose Neuromorphic Sensor based on Spiketrum Algorithm: Hardware Details and Real-life Applications. CoRR MHD Anas Alsakkal, Runze Wang, Jayawan H. B. Wijekoon, Piotr Dudek
2025	—	`conf`	Demo : Point-Feature Tracking for Pixel Processor Arrays. CVPR Workshops Laurie Bose, Piotr Dudek
2025	A*	`conf`	Descriptor-In-Pixel : Point-Feature Tracking For Pixel Processor Arrays. CVPR Laurie Bose, Jianing Chen, Piotr Dudek
2025	C	`conf`	Design and FPGA Realization of QUBO hardware accelerator for MAX-CUT problem. ISCAS Maciej Lewandowski, Piotr Dudek
2025	C	`conf`	Digital Implementation of a Spiking/Bursting Neuron Model with Low Resources. ISCAS Ziyao Zhang, Piotr Dudek, Jayawan H. B. Wijekoon
2025	J	`jnl`	Implementation of Low-Cost Time-to-Digital Converter in the Off-the-Shelf Radiation-Tolerant Space-Grade FPGA. IEEE Trans. Aerosp. Electron. Syst. Jacek Goczkowski, Marek Wójcikowski, Piotr Dudek
2024	J	`jnl`	Factor Machine: Mixed-signal Architecture for Fine-Grained Graph-Based Computing. CoRR Piotr Dudek
2024	J	`jnl`	Mapping Image Transformations Onto Pixel Processor Arrays. CoRR Laurie Bose, Piotr Dudek
2024	A*	`conf`	PixelRNN: In-pixel Recurrent Neural Networks for End-to-end-optimized Perception with Neural Sensors. CVPR Haley M. So, Laurie Bose, Piotr Dudek, Gordon Wetzstein
2023	—	`conf`	Live Demonstration: SCAMP-7. CVPR Workshops Laurie Bose, Piotr Dudek, Stephen J. Carey, Jianing Chen
2023	J	`jnl`	PixelRNN: In-pixel Recurrent Neural Networks for End-to-end-optimized Perception with Neural Sensors. CoRR Haley M. So, Laurie Bose, Piotr Dudek, Gordon Wetzstein
2022	B	`conf`	MantissaCam: Learning Snapshot High-dynamic-range Imaging with Perceptually-based In-pixel Irradiance Encoding. ICCP Haley M. So, Julien N. P. Martel, Gordon Wetzstein, Piotr Dudek
2022	—	`conf`	Pixel Processor Arrays For Low Latency Gaze Estimation. VR Workshops Laurie Bose, Jianing Chen, Stephen J. Carey, Piotr Dudek
2022	J	`jnl`	Sensor-level computer vision with pixel processor arrays for agile robots. Sci. Robotics Piotr Dudek, Tom Richardson, Laurie Bose, Stephen J. Carey, Jianing Chen, Colin Greatwood, Yanan Liu, Walterio W. Mayol-Cuevas
2021	J	`jnl`	Agile reactive navigation for a non-holonomic mobile robot using a pixel processor array. IET Image Process. Yanan Liu, Laurie Bose, Colin Greatwood, Jianing Chen, Rui Fan, Thomas Richardson, Stephen J. Carey, Piotr Dudek, Walterio W. Mayol-Cuevas
2021	J	`jnl`	Bringing A Robot Simulator to the SCAMP Vision System. CoRR Yanan Liu, Jianing Chen, Laurie Bose, Piotr Dudek, Walterio W. Mayol-Cuevas
2021	J	`jnl`	Direct Servo Control from In-Sensor CNN Inference with A Pixel Processor Array. CoRR Yanan Liu, Jianing Chen, Laurie Bose, Piotr Dudek, Walterio W. Mayol-Cuevas
2021	J	`jnl`	MantissaCam: Learning Snapshot High-dynamic-range Imaging with Perceptually-based In-pixel Irradiance Encoding. CoRR Haley M. So, Julien N. P. Martel, Piotr Dudek, Gordon Wetzstein
2020	C	`conf`	A Mixed-Signal Spatio-Temporal Signal Classifier for On-Sensor Spike Sorting. ISCAS Germain Haessig, Daniel García-Lesta, Gregor Lenz, Ryad Benosman, Piotr Dudek
2020	J	`jnl`	Agile Reactive Navigation for A Non-Holonomic Mobile Robot Using A Pixel Processor Array. CoRR Yanan Liu, Laurie Bose, Colin Greatwood, Jianing Chen, Rui Fan, Thomas S. Richardson, Stephen J. Carey, Piotr Dudek, Walterio W. Mayol-Cuevas
2020	—	`conf`	Fully Embedding Fast Convolutional Networks on Pixel Processor Arrays. ECCV (29) Laurie Bose, Piotr Dudek, Jianing Chen, Stephen J. Carey, Walterio W. Mayol-Cuevas
2020	J	`jnl`	Fully Embedding Fast Convolutional Networks on Pixel Processor Arrays. CoRR Laurie Bose, Jianing Chen, Stephen J. Carey, Piotr Dudek, Walterio W. Mayol-Cuevas
2020	A	`conf`	High-speed Light-weight CNN Inference via Strided Convolutions on a Pixel Processor Array. BMVC Yanan Liu, Laurie Bose, Jianing Chen, Stephen J. Carey, Piotr Dudek, Walterio W. Mayol-Cuevas
2020	C	`conf`	Lessons Learned the Hard Way. ISCAS Tobi Delbruck, Ibrahim Abe M. Elfadel, Shahzad Muzaffar, Germain Haessig, Bo Wang, Amine Bermak, Rui Graca, Luis A. Camuñas-Mesa, Bathiya Senevirathna, Pamela Abshire, Bernabé Linares-Barranco, Saeed Afshar, Shih-Chii Liu, Runchun Mark Wang, Piotr Dudek, Stephen J. Carey, José M. de la Rosa, Marc Dandin, Sheung Lu, Vincent Frick, Teresa Serrano-Gotarredona, Paula López, Melika Payvand, Advait Madhavan, Eric R. Fossum, Juan Camilo Vasquez Tieck, Ian Williams, Yan Liu, Timothy G. Constandinou, Alexander Serb, Ricardo Carmona-Galán, Robert Nawrocki, Walter D. Leon-Salas
2020	C	`conf`	Live Demonstration: CNN Inference on the Focal Plane with a Pixel Processor Array. ISCAS Stephen J. Carey, Laurie Bose, Thomas S. Richardson, Walterio W. Mayol-Cuevas, Jianing Chen, Piotr Dudek
2020	J	`jnl`	Neural Sensors: Learning Pixel Exposures for HDR Imaging and Video Compressive Sensing With Programmable Sensors. IEEE Trans. Pattern Anal. Mach. Intell. Julien N. P. Martel, Lorenz K. Müller, Stephen J. Carey, Piotr Dudek, Gordon Wetzstein
2020	A*	`conf`	Proximity Estimation Using Vision Features Computed On Sensor. ICRA Jianing Chen, Yanan Liu, Stephen J. Carey, Piotr Dudek
2020	J	`jnl`	Visual Odometry Using Pixel Processor Arrays for Unmanned Aerial Systems in GPS Denied Environments. Frontiers Robotics AI Alexander McConville, Laurie Bose, Robert Clarke, Walterio W. Mayol-Cuevas, Jianing Chen, Colin Greatwood, Stephen J. Carey, Piotr Dudek, Thomas Richardson
2019	A*	`conf`	A Camera That CNNs: Towards Embedded Neural Networks on Pixel Processor Arrays. ICCV Laurie Bose, Piotr Dudek, Jianing Chen, Stephen J. Carey, Walterio W. Mayol-Cuevas
2019	J	`jnl`	A Camera That CNNs: Towards Embedded Neural Networks on Pixel Processor Arrays. CoRR Laurie Bose, Jianing Chen, Stephen J. Carey, Piotr Dudek, Walterio W. Mayol-Cuevas
2019	—	`conf`	Live Demonstration: Digit Recognition on Pixel Processor Arrays. CVPR Workshops Laurie Bose, Jianing Chen, Stephen J. Carey, Piotr Dudek, Walterio W. Mayol-Cuevas
2018	A	`conf`	Perspective Correcting Visual Odometry for Agile MAVs using a Pixel Processor Array. IROS Colin Greatwood, Laurie Bose, Thomas Richardson, Walterio W. Mayol-Cuevas, Jianing Chen, Stephen J. Carey, Piotr Dudek
2018	J	`jnl`	Real-Time Depth From Focus on a Programmable Focal Plane Processor. IEEE Trans. Circuits Syst. I Regul. Pap. Julien N. P. Martel, Lorenz K. Müller, Stephen J. Carey, Jonathan Müller, Yulia Sandamirskaya, Piotr Dudek
2018	—	`conf`	Scamp5d Vision System and Development Framework. ICDSC Jianing Chen, Stephen J. Carey, Piotr Dudek
2017	C	`conf`	High-speed depth from focus on a programmable vision chip using a focus tunable lens. ISCAS Julien N. P. Martel, Lorenz K. Müller, Stephen J. Carey, Piotr Dudek
2017	C	`conf`	Live demonstration: Depth from focus on a focal plane processor using a focus tunable liquid lens. ISCAS Julien N. P. Martel, Lorenz K. Müller, Stephen J. Carey, Jonathan Müller, Yulia Sandamirskaya, Piotr Dudek
2017	A	`conf`	Tracking control of a UAV with a parallel visual processor. IROS Colin Greatwood, Laurie Bose, Thomas S. Richardson, Walterio W. Mayol-Cuevas, Jianing Chen, Stephen J. Carey, Piotr Dudek
2017	A*	`conf`	Visual Odometry for Pixel Processor Arrays. ICCV Laurie Bose, Jianing Chen, Stephen J. Carey, Piotr Dudek, Walterio W. Mayol-Cuevas
2016	—	`conf`	A Demonstration of Tracking using Dynamic Neural Fields on a Programmable Vision Chip: Demo. ICDSC Julien N. P. Martel, Yulia Sandamirskaya, Piotr Dudek
2016	C	`conf`	Parallel HDR tone mapping and auto-focus on a cellular processor array vision chip. ISCAS Julien N. P. Martel, Lorenz K. Müller, Stephen J. Carey, Piotr Dudek
2015	C	`conf`	An event-driven massively parallel fine-grained processor array. ISCAS Declan Walsh, Piotr Dudek
2015	B	`conf`	Gradient-descent-based learning in memristive crossbar arrays. IJCNN Manu V. Nair, Piotr Dudek
2015	—	`conf`	Pixel interlacing to trade off the resolution of a cellular processor array against more registers. ECCTD Julien N. P. Martel, Miguel Chau, Matthew Cook, Piotr Dudek
2015	C	`conf`	Toward joint approximate inference of visual quantities on cellular processor arrays. ISCAS Julien N. P. Martel, Miguel Chau, Piotr Dudek, Matthew Cook
2015	J	`jnl`	Trigger-Wave Asynchronous Cellular Logic Array for Fast Binary Image Processing. IEEE Trans. Circuits Syst. I Regul. Pap. Przemyslaw Mroszczyk, Piotr Dudek
2014	—	`conf`	A Fast Self-Tuning Background Subtraction Algorithm. CVPR Workshops Bin Wang, Piotr Dudek
2014	C	`conf`	Characterization of processing errors on analog fully-programmable cellular sensor-processor arrays. ISCAS Stephen J. Carey, Ákos Zarándy, Piotr Dudek
2014	C	`conf`	Live demonstration: A sensor-processor array integrated circuit for high-speed real-time machine vision. ISCAS Stephen J. Carey, David Robert Wallace Barr, Bin Wang, Alexey Lopich, Piotr Dudek
2014	C	`conf`	The accuracy and scalability of continuous-time Bayesian inference in analogue CMOS circuits. ISCAS Przemyslaw Mroszczyk, Piotr Dudek
2014	J	`jnl`	Tunable CMOS Delay Gate With Improved Matching Properties. IEEE Trans. Circuits Syst. I Regul. Pap. Przemyslaw Mroszczyk, Piotr Dudek
2013	B	`conf`	A Smart Surface Simulation Environment. SMC David Robert Wallace Barr, Declan Walsh, Piotr Dudek
2013	—	`conf`	A general-purpose vision processor with 160×80 pixel-parallel SIMD processor array. CICC Alexey Lopich, Piotr Dudek
2013	B	`conf`	AMBER: Adapting multi-resolution background extractor. ICIP Bin Wang, Piotr Dudek
2013	J	`jnl`	Low power high-performance smart camera system based on SCAMP vision sensor. J. Syst. Archit. Stephen J. Carey, David Robert Wallace Barr, Piotr Dudek
2013	—	`conf`	Metachronal Waves in Cellular Automata: Cilia-Like Manipulation in Actuator Arrays. NICSO Ioannis Georgilas, Andrew Adamatzky, David Robert Wallace Barr, Piotr Dudek, Chris Melhuish
2013	—	`conf`	Trigger-wave propagation in arbitrary metrics in asynchronous cellular logic arrays. ECCTD Przemyslaw Mroszczyk, Piotr Dudek
2013	—	`conf`	Tunable CMOS delay gate with reduced impact of fabrication mismatch on timing parameters. NEWCAS Przemyslaw Mroszczyk, Piotr Dudek
2012	A	`conf`	A field programmable array core for image processing (abstract only). FPGA Declan Walsh, Piotr Dudek
2012	—	`conf`	Development of robot self-identification based on visuomotor prediction. ICDL-EPIROB Tao Zhou, Piotr Dudek, Bertram E. Shi
2012	C	`conf`	Heterogeneous neurons and plastic synapses in a reconfigurable cortical neural network IC. ISCAS Jayawan H. B. Wijekoon, Piotr Dudek
2012	—	`conf`	Mixed signal SIMD cellular processor array vision chip operating at 30, 000 fps. ICECS Stephen J. Carey, David Robert Wallace Barr, Bin Wang, Alexey Lopich, Piotr Dudek
2012	C	`conf`	Trigger-wave collision detecting asynchronous cellular logic array for fast image skeletonization. ISCAS Przemyslaw Mroszczyk, Piotr Dudek
2011	J	`jnl`	A SIMD Cellular Processor Array Vision Chip With Asynchronous Processing Capabilities. IEEE Trans. Circuits Syst. I Regul. Pap. Alexey Lopich, Piotr Dudek
2011	C	`conf`	A processor element for a mixed signal cellular processor array vision chip. ISCAS Stephen J. Carey, Alexey Lopich, Piotr Dudek
2011	C	`conf`	Analogue CMOS circuit implementation of a dopamine modulated synapse. ISCAS Jayawan H. B. Wijekoon, Piotr Dudek
2011	C	`conf`	Architecture and design of a programmable 3D-integrated cellular processor array for image processing. VLSI-SoC Alexey Lopich, Piotr Dudek
2011	J	`jnl`	Asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array. Int. J. Circuit Theory Appl. Alexey Lopich, Piotr Dudek
2011	C	`conf`	Confession session: Learning from others mistakes. ISCAS Pamela Abshire, Amine Bermak, Raphael Berner, Gert Cauwenberghs, Shoushun Chen, Jennifer Blain Christen, Timothy G. Constandinou, Eugenio Culurciello, Marc Dandin, Timir Datta, Tobi Delbruck, Piotr Dudek, Amir Eftekhar, Ralph Etienne-Cummings, Giacomo Indiveri, Matthew K. Law, Bernabé Linares-Barranco, Jonathan Tapson, Wei Tang, Yiming Zhai
2011	—	`conf`	Demonstration of a low power image processing system using a SCAMP3 vision chip. ICDSC Stephen J. Carey, David Robert Wallace Barr, Piotr Dudek
2011	C	`conf`	Live demonstration: Real-time image processing on ASPA2 vision system. ISCAS Alexey Lopich, David Robert Wallace Barr, Bin Wang, Piotr Dudek
2011	B	`conf`	Self-Organizing Neural Population Coding for improving robotic visuomotor coordination. IJCNN Tao Zhou, Piotr Dudek, Bertram E. Shi
2010	C	`conf`	An 80×80 general-purpose digital vision chip in 0.18μm CMOS technology. ISCAS Alexey Lopich, Piotr Dudek
2010	—	`conf`	Using Reinforcement Learning to Guide the Development of Self-organised Feature Maps for Visual Orienting. ICANN (2) Kevin Brohan, Kevin N. Gurney, Piotr Dudek
2009	—	`conf`	A pixel-parallel cellular processor array in a stacked three-layer 3D silicon-on-insulator technology. ECCTD Piotr Dudek, Alexey Lopich, Viktor Gruev
2009	J	`jnl`	APRON: A Cellular Processor Array Simulation and Hardware Design Tool. EURASIP J. Adv. Signal Process. David Robert Wallace Barr, Piotr Dudek
2009	J	`jnl`	Hardware Implementation of Skeletonization Algorithm for Parallel Asynchronous Image Processing. J. Signal Process. Syst. Alexey Lopich, Piotr Dudek
2008	C	`conf`	ASPA: Focal Plane digital processor array with asynchronous processing capabilities. ISCAS Alexey Lopich, Piotr Dudek
2008	—	`conf`	Cellular automata and non-static image processing for embodied robot systems on a massively parallel processor array. Automata Martin Hülse, David Robert Wallace Barr, Piotr Dudek
2008	J	`jnl`	Compact silicon neuron circuit with spiking and bursting behaviour. Neural Networks Jayawan H. B. Wijekoon, Piotr Dudek
2008	J	`jnl`	Fast retinal vessel tree extraction: A pixel parallel approach. Int. J. Circuit Theory Appl. Carmen Alonso-Montes, David López Vilariño, Piotr Dudek, Manuel G. Penedo
2008	C	`conf`	Focal-plane moving object segmentation for realtime video surveillance. ISCAS David López Vilariño, Piotr Dudek, Diego Cabello
2008	C	`conf`	Integrated circuit implementation of a cortical neuron. ISCAS Jayawan H. B. Wijekoon, Piotr Dudek
2008	B	`conf`	Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks. FPL Jim Harkin, Fearghal Morgan, Steve Hall, Piotr Dudek, Thomas Dowrick, Liam McDaid
2007	C	`conf`	Evolution of Pixel Level Snakes towards an efficient hardware implementation. ISCAS David López Vilariño, Piotr Dudek
2007	—	`conf`	Implementation of an asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array. ECCTD Alexey Lopich, Piotr Dudek
2007	B	`conf`	Implementation of multi-layer leaky integrator networks on a cellular processor array. IJCNN David Robert Wallace Barr, Piotr Dudek, Jonathan M. Chambers, Kevin N. Gurney
2007	—	`conf`	On chip implementation of a pixel-parallel approach for retinal vessel tree extraction. ECCTD Carmen Alonso-Montes, Piotr Dudek, David López Vilariño, Manuel G. Penedo
2007	B	`conf`	Spiking and Bursting Firing Patterns of a Compact VLSI Cortical Neuron Circuit. IJCNN Jayawan H. B. Wijekoon, Piotr Dudek
2006	J	`jnl`	An asynchronous cellular logic network for trigger-wave image processing on fine-grain massively parallel arrays. IEEE Trans. Circuits Syst. II Express Briefs Piotr Dudek
2006	C	`conf`	Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing. ISCAS Alexey Lopich, Piotr Dudek
2006	—	`conf`	Simple Analogue VLSI Circuit of a Cortical Neuron. ICECS Jayawan H. B. Wijekoon, Piotr Dudek
2005	J	`jnl`	A general-purpose processor-per-pixel analog SIMD vision chip. IEEE Trans. Circuits Syst. I Regul. Pap. Piotr Dudek, Peter J. Hicks
2005	—	`conf`	An area and power efficient discrete-time chaos generator circuit. ECCTD Piotr Dudek, V. D. Juncu
2005	—	`conf`	Architecture of asynchronous cellular processor array for image skeletonization. ECCTD Aliaksei Lopich, Piotr Dudek
2005	—	`conf`	Implementation of SIMD vision chip with 128×128 array of analogue processing elements. ISCAS (6) Piotr Dudek
2004	—	`conf`	A 39×48 general-purpose focal-plane processor array integrated circuit. ISCAS (5) Piotr Dudek
2003	—	`conf`	A flexible global readout architecture for an analogue SIMD vision chip. ISCAS (3) Piotr Dudek
2001	—	`conf`	An analogue SIMD focal-plane processor array. ISCAS (4) Piotr Dudek, Peter J. Hicks
2000	C	`conf`	A CMOS general-purpose sampled-data analogue microprocessor. ISCAS Piotr Dudek, Peter J. Hicks
2000	J	`jnl`	A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line. IEEE J. Solid State Circuits Piotr Dudek, Stanislaw Szczepanski, John V. Hatfield