Pingfen Lin

13 papers Journal 8Unranked 5
YearRankTypeTitle / Venue / Authors
2013 J jnl
1.1-V, 8-bit, 12 MS/s asynchronous reference-free successive-approximation-register analogue-todigital converter in 0.18 μm CMOS with separated capacitor arrays.
IET Circuits Devices Syst.
Guanzhong Huang, Pingfen Lin
2013 J jnl
A 0.8 V 48 μW 82 dB SNDR 10-kHz BANDWIDTH ΣΔ MODULATOR IN 0.13-μM CMOS.
J. Circuits Syst. Comput.
Wei Lang, Peiyuan Wan, Pingfen Lin
2013 J jnl
A TIME-DOMAIN 1.0-V/0.8-MW 6-BIT 125 MS/S FLASH ADC IN 65 NM CMOS.
J. Circuits Syst. Comput.
Guanzhong Huang, Pingfen Lin
2012 J jnl
A 15fJ/conversion-step 8-bit 50 MS/s asynchronous SAR ADC with efficient charge recycling technique.
Microelectron. J.
Guanzhong Huang, Pingfen Lin
2012 — conf
A 5-bit 125-MS/s 367-µW ADC in 65-nm CMOS.
MWSCAS
Guanzhong Huang, Pingfen Lin
2011 — conf
A 1.2-V 250-MS/s 8-bit pipelined ADC in 0.13-µm CMOS.
ASICON
Peiyuan Wan, Wei Lang, Di Fang, Wei Cui, Pingfen Lin
2011 — conf
A 48-mW, 12-bit, 150-MS/s pipelined ADC with digital calibration in 65nm CMOS.
CICC
Bei Peng, Guanzhong Huang, Hao Li, Peiyuan Wan, Pingfen Lin
2010 — conf
A 5.8-mW, 20-MHz, 4th-order programmable elliptic filter achieving over -80-dB IM3.
CICC
Peiyuan Wan, Yun Chiu, Pingfen Lin
2010 J jnl
A Virtual-ADC Digital Background Calibration Technique for Multistage A/D Conversion.
IEEE Trans. Circuits Syst. II Express Briefs
Bei Peng, Hao Li, Seung-Chul Lee, Pingfen Lin, Yun Chiu
2010 — conf
A fast bootstrapped switch for high-speed high-resolution A/D converter.
APCCAS
Guanzhong Huang, Pingfen Lin
2010 J jnl
An Offset Double Conversion Technique for Digital Calibration of Pipelined ADCs.
IEEE Trans. Circuits Syst. II Express Briefs
Bei Peng, Hao Li, Pingfen Lin, Yun Chiu
2008 J jnl
A new lock detector for Gardner's timing recovery method.
IEEE Trans. Consumer Electron.
Huang Lou, Pingfen Lin
2008 J jnl
Hybrid carrier recovery, blind equalization for high-order QAM signal constellations.
IEEE Trans. Consumer Electron.
Huang Lou, Pingfen Lin