Pingda Guan

16 papers Journal 8Unranked 8
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 24.5-45.2-GHz Low-Jitter Compact Differentially Injection-Locked Clock Multiplier With Folded-Inductor-Based Magnetic-Flux Cancellation.
IEEE J. Solid State Circuits
Feifan Hong, Jiawen Chen, Pingda Guan, Sayan Kumar, Robert Bogdan Staszewski, Teerachot Siriburanon
2025 J jnl
A 26-Gb/s 140-GHz OOK CMOS Transmitter and Receiver Chipset for High-Speed Wireless and Dielectric Waveguide Communication.
IEEE J. Solid State Circuits
Qiuyu Peng, Haikun Jia, Ran Fang, Pingda Guan, Mingxing Deng, Jiamin Xue, Wei Deng, Xin Liang, Baoyong Chi
2025 — conf
A High-Linearity 250-MHz Constant-Slope Digital-to-Time Converter.
ICECS
Peng Chen, Viet Nguyen, Hongtao Huang, Xiongchuan Huang, Feifan Hong, Pingda Guan, Robert Bogdan Staszewski
2025 J jnl
A Transformer-Based Series-Resonance CMOS VCO.
IEEE J. Solid State Circuits
Shiwei Zhang, Wei Deng, Haikun Jia, Hongzhuo Liu, Shiyan Sun, Pingda Guan, Zhihua Wang, Baoyong Chi
2024 J jnl
A Fully Integrated QPSK/16-QAM D-Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing Digital Interfaces.
IEEE J. Solid State Circuits
Pingda Guan, Ruichang Ma, Haikun Jia, Wei Deng, Mingxing Deng, Jiamin Xue, Angxiao Yan, Shiyan Sun, Qiuyu Peng, Teerachot Siriburanon, Robert Bogdan Staszewski, Zhihua Wang, Baoyong Chi
2023 — conf
A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS.
CICC
Shiwei Zhang, Wei Deng, Haikun Jia, Hongzhuo Liu, Shiyan Sun, Pingda Guan, Baoyong Chi
2023 — conf
A 25.0-to-35.9GHz Dual-Layer Quad-Core Dual-Mode VCO with 189.1dBc/Hz FoM and 200.2dBc/Hz FoMT at 1MHz Offset in 65nm CMOS.
CICC
Pingda Guan, Haikun Jia, Wei Deng, Ruichang Ma, Huabing Liao, Zhihua Wang, Baoyong Chi
2023 J jnl
A D-Band Joint Radar-Communication CMOS Transceiver.
IEEE J. Solid State Circuits
Wei Deng, Zipeng Chen, Haikun Jia, Pingda Guan, Taikun Ma, Angxiao Yan, Shiyan Sun, Xiangrong Huang, Guopei Chen, Ruichang Ma, Shengnan Dong, Luqiang Duan, Zhihua Wang, Baoyong Chi
2023 — conf
A Fully Integrated Bit-to-Bit 24/48Gb/s QPSK/16-QAM D-Band Transceiver with Mixed-Signal Baseband in 28nm CMOS Technology.
A-SSCC
Pingda Guan, Haikun Jia, Wei Deng, Ruichang Ma, Mingxing Deng, Jiamin Xue, Angxiao Yan, Shiyan Sun, Zhihua Wang, Baoyong Chi
2023 J jnl
A Low-Phase-Noise Quad-Core Millimeter-Wave Fundamental VCO Using Circular Triple-Coupled Transformer in 65-nm CMOS.
IEEE J. Solid State Circuits
Haikun Jia, Pingda Guan, Wei Deng, Zhihua Wang, Baoyong Chi
2021 — conf
A 122-168GHz Radar/Communication Fusion-Mode Transceiver with 30GHz Chirp Bandwidth, 13dBm Psat, and 8.3dBm OP1dB in 28nm CMOS.
VLSI Circuits
Zipeng Chen, Wei Deng, Haikun Jia, Pingda Guan, Taikun Ma, Shiyan Sun, Xiangrong Huang, Guopei Chen, Ruichang Ma, Shengnan Dong, Luqiang Duan, Zhihua Wang, Baoyong Chi
2021 — conf
A 33.5-37.5 GHz 4-Element Phased-Array Transceiver Front-End with High-Accuracy Low-Variation 6-bit Resolution 360° Phase Shift and 0~31.5 dB Gain Control in 65 nm CMOS.
A-SSCC
Pingda Guan, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi
2021 — conf
A 60GHz 186.5dBc/Hz FoM Quad-Core Fundamental VCO Using Circular Triple-Coupled Transformer with No Mode Ambiguity in 65nm CMOS.
ISSCC
Haikun Jia, Wei Deng, Pingda Guan, Zhihua Wang, Baoyong Chi
2021 — conf
An Ultra-Compact 16-to-45 GHz Power Amplifier within A Single Inductor Footprint Using Folded Transformer Technique.
CICC
Pingda Guan, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi
2020 J jnl
A U-Band PLL Using Implicit Distributed Resonators for Sub-THz Wireless Transceivers in 40 nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Zipeng Chen, Wei Deng, Haikun Jia, Yibo Liu, Jianxi Wu, Pingda Guan, Jinyu Zhu, Luhong Mao, Zhihua Wang, Baoyong Chi
2019 J jnl
A G-Band Wideband Bidirectional Transceiver Front-End in 40-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Yibo Liu, Taikun Ma, Pingda Guan, Luhong Mao, Baoyong Chi