Ping Lu

20 papers C 3Journal 7Unranked 10
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 6.8-GHz Fractional-N Pulse-Shaper-Based PLL Achieving -269.9-dB FoM
IEEE Trans. Circuits Syst. I Regul. Pap.
Haoyuan Gao, Yan Liu, Peifang Wu, Jiao Liu, Yiyun Mao, Xinyi Lin, Rui Yin, Ping Lu, Long Kong, Na Yan
2025 J jnl
An All-Digital Spread-Spectrum Clock Generator With Feedforward Gain Calibration for LPWAN Chirp Transmission System.
IEEE Trans. Circuits Syst. II Express Briefs
Yiyun Mao, Haoyuan Gao, Jin Shao, Xinyi Lin, Peifang Wu, Ping Lu, Hao Xu, Na Yan
2024 J jnl
A 10-bit 563-fs Step Constant-Slope Digital-to-Time Converter in 40-nm CMOS With Nonlinearity Cancellation and Range Extension Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yan Liu, Haoyuan Gao, Hao Xu, Ping Lu, Na Yan
2020 J jnl
A Time-Domain 147fs
IEEE Trans. Circuits Syst. I Regul. Pap.
Ying Wu, Ping Lu, Robert Bogdan Staszewski
2017 J jnl
A 3.5-6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH ΔΣ-TDC for Low In-Band Phase Noise.
IEEE J. Solid State Circuits
Ying Wu, Mina Shahmohammadi, Yue Chen, Ping Lu, Robert Bogdan Staszewski
2016 J jnl
A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter With Digital Calibration.
IEEE Trans. Circuits Syst. II Express Briefs
Ping Lu, Ying Wu, Pietro Andreani
2016 — conf
A 3.5-6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise.
ESSCIRC
Ying Wu, Mina Shahmohammadi, Yue Chen, Ping Lu, Robert Bogdan Staszewski
2015 — conf
A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise.
NORCAS
Ahmed Mahmoud, Pietro Andreani, Ping Lu
2014 C conf
A 1-1 MASH 2-D vernier time-to-digital converter with 2
ISCAS
Ping Lu, Pietro Andreani
2014 — conf
A 9-bit 1-MS/s 7-μW SAR ADC for ultra low power radio.
NORCHIP
Ji Wang, Manuel Bejarano Carmona, Helgi Hall, Dejan Radjen, Ping Lu
2013 C conf
A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing.
ISCAS
Dawei Ye, Ping Lu, Pietro Andreani, Ronan A. R. van der Zee
2012 J jnl
A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps.
IEEE J. Solid State Circuits
Ping Lu, Antonio Liscidini, Pietro Andreani
2012 C conf
A 90nm CMOS digital PLL based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter.
ISCAS
Ping Lu, Ying Wu, Pietro Andreani
2012 — conf
A 90nm CMOS gated-ring-oscillator-based 2-dimension Vernier time-to-digital converter.
NORCHIP
Ping Lu, Pietro Andreani, Antonio Liscidini
2011 — conf
A 0.13µm CMOS ΔΣ PLL FM transmitter.
NORCHIP
Ying Wu, Xiaodong Liu, Dawei Ye, Vijay Viswam, Lin Zhu, Ping Lu, Dejan Radjen, Henrik Sjöland
2011 — conf
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS.
NORCHIP
Mohammed Abdulaziz, Muhammad Shakir, Ping Lu, Pietro Andreani
2011 — conf
A 90nm CMOS gated-ring-oscillator-based Vernier time-to-digital converter for DPLLs.
ESSCIRC
Ping Lu, Pietro Andreani, Antonio Liscidini
2011 — conf
A digital PLL with a multi-delay coarse-fine TDC.
NORCHIP
Ying Wu, Ping Lu, Pietro Andreani
2011 — conf
A mixed mode design flow for multi GHz ADPLLs.
NORCHIP
Muhammad Shakir, Mohammed Abdulaziz, Ping Lu, Pietro Andreani
2009 — conf
A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator.
SoCC
Ping Lu, Danfeng Chen, Fan Ye, Junyan Ren