Ping-Ying Wang

14 papers A 1C 2Journal 2Unranked 9
YearRankTypeTitle / Venue / Authors
2015 — conf
10.8 A wideband fractional-N ring PLL using a near-ground pre-distorted switched-capacitor loop filter.
ISSCC
Che-Fu Liang, Ping-Ying Wang
2015 — conf
A 1V fractional-N PLL with nonlinearity-insensitive modulator.
A-SSCC
Yi-Chieh Huang, Che-Fu Liang, Ping-Ying Wang
2014 — conf
15.3 A 2.4GHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO.
ISSCC
Yi-Chieh Huang, Che-Fu Liang, Hsien-Sheng Huang, Ping-Ying Wang
2012 J jnl
An All-Digital Jitter Tolerance Measurement Technique for CDR Circuits.
IEEE Trans. Circuits Syst. II Express Briefs
Yi-Chieh Huang, Ping-Ying Wang, Shen-Iuan Liu
2011 A conf
An all-digital built-in self-test technique for transfer function characterization of RF PLLs.
DATE
Ping-Ying Wang, Hsiu-Ming Chang, Kwang-Ting Cheng
2010 — conf
All digital modulation bandwidth extension technique for narrow bandwidth analog fractional-N PLL.
ESSCIRC
Ping-Ying Wang, Chia-Huang Fu
2009 J jnl
A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes.
IEEE J. Solid State Circuits
Ping-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, Hsiu-Ming (Sherman) Chang
2008 — conf
A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE.
ISSCC
Hsiang-Hui Chang, Ping-Ying Wang, Jing-Hong Conan Zhan, Bing-Yu Hsieh
2008 C conf
A charge pump-based direct frequency modulator.
ISCAS
Ping-Ying Wang, Hsiu-Ming Chang
2008 — conf
A fractional spur reduction technique for RF TDC-based all digital PLLs.
ESSCIRC
Ping-Ying Wang, Hsiang-Hui Chang, Jing-Hong Conan Zhan
2008 — conf
An analog enhanced all digtial RF fractional-N PLL with self-calibrated capability.
CICC
Ping-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, Bing-Yu Hsieh
2007 — conf
RTL-based Clock Recovery Architecture with All-Digital Duty-Cycle Correction.
ISSCC
Ping-Ying Wang, Meng-Ta Yang, Shang-Ping Chen, Meng-Hsueh Lin, Jing-Bing Yang
2006 C conf
Chaos in delay locked loop.
ISCAS
Ping-Ying Wang, C.-H. Chou, Hsueh-Wu Kao
2005 — conf
A phase locked loop with a mixed mode loop filter for clock/data recovery in optical disc drives.
ISCAS (5)
Ping-Ying Wang, Hsiang Ji Hsieh, Yung-Yu Lin, Meng-Ta Yang, Hsueh-Wu Kao