Ping-Hung Yuh

20 papers A* 3A 5Journal 8Unranked 4
YearRankTypeTitle / Venue / Authors
2015 — conf
Accurate 3-D capacitance extractions for advanced nanometer CMOS nodes.
VLSI-DAT
Keh-Jeng Chang, Shih-Hao Lee, Kuo-Fu Lee, Ping-Hung Yuh, Ho-Che Yu, Wen-Cheng Huang, Victor C. Y. Chang
2012 J jnl
Optimized 3D Network-on-Chip Design Using Simulated Allocation.
ACM Trans. Design Autom. Electr. Syst.
Pingqiang Zhou, Ping-Hung Yuh, Sachin S. Sapatnekar
2011 — conf
A SAT-based routing algorithm for cross-referencing biochips.
SLIP
Ping-Hung Yuh, Cliff Chiung-Yu Lin, Tsung-Wei Huang, Tsung-Yi Ho, Chia-Lin Yang, Yao-Wen Chang
2010 — conf
Application-specific 3D Network-on-Chip design using simulated allocation.
ASP-DAC
Pingqiang Zhou, Ping-Hung Yuh, Sachin S. Sapatnekar
2009 J jnl
A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang
2009 J jnl
Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs.
ACM Trans. Design Autom. Electr. Syst.
Ping-Hung Yuh, Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin
2009 J jnl
T-trees: A tree-based representation for temporal and three-dimensional floorplanning.
ACM Trans. Design Autom. Electr. Syst.
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2008 A* conf
A progressive-ILP based routing algorithm for cross-referencing biochips.
DAC
Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang
2008 J jnl
BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2008 J jnl
MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Tien-Yueh Liu
2007 A conf
BioRoute: a network-flow based routing algorithm for digital microfluidic biochips.
ICCAD
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2007 A* conf
MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs.
DAC
Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Denny Liu
2007 J jnl
Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation.
ACM J. Emerg. Technol. Comput. Syst.
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2007 A conf
Post-placement leakage optimization for partially dynamically reconfigurable FPGAs.
ISLPED
Chi-Feng Li, Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2007 J jnl
Temporal floorplanning using the three-dimensional transitive closure subGraph.
ACM Trans. Design Autom. Electr. Syst.
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2006 A* conf
Placement of digital microfluidic biochips using the t-tree formulation.
DAC
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2005 A conf
A routing algorithm for flip-chip design.
ICCAD
Jia-Wei Fang, I-Jye Lin, Ping-Hung Yuh, Yao-Wen Chang, Jyh-Herng Wang
2005 A conf
Joint exploration of architectural and physical design spaces with thermal consideration.
ISLPED
Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang
2004 — conf
Temporal floorplanning using 3D-subTCG.
ASP-DAC
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen
2004 A conf
Temporal floorplanning using the T-tree formulation.
ICCAD
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang