Ping-Hsuan Hsieh

42 papers B 1C 5Journal 18Unranked 18

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 2.16-pJ/b 112-Gb/s PAM-4 Transceiver With Time-Interleaved 2-b/3-b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28-nm CMOS. IEEE J. Solid State Circuits Yen-Po Lin, Pen-Jui Peng, Chun-Chang Lu, Po-Ting Shen, Yun-Cheng Jao, Ping-Hsuan Hsieh
2026	J	`jnl`	Analog Convolution Circuit System Implemented With Capacitor Array Superposition. IEEE Open J. Circuits Syst. Chung-Yi Wang, Ping-Hsuan Hsieh, Zi-Cin Wang
2025	—	`conf`	15.4 A Neuroprosthetic SoC with Sensory Feedback Featuring Frequency-Splitting-Based Wireless Power Transfer with 200Mb/s 0.67pJ/b Backscatter Data Uplink and Unsupervised Multi-Class Spike Sorting. ISSCC Yu Huang, Bowen Liu, Yuhan Hou, Jianxiong Xu, Hao You, Ashley Hung, Swarnava Ghosh, Eric Liu, Naize Yang, Junyu Ma, Hanfeng Cai, Laura Kondrataviciute, Qiaosong Deng, Suneil K. Kalia, Andrew G. Richardson, Ping-Hsuan Hsieh, Roman Genov, Xilin Liu
2025	—	`conf`	A Logic-Compatible 2T Gain-Cell eDRAM in 40-nm CMOS Process. NewCAS Chia-Yu Chu, Ping-Hsuan Hsieh, Chung-Yi Wang
2025	J	`jnl`	Economic analysis of an AI-enabled ECG alert system: impact on mortality outcomes from a pragmatic randomized trial. npj Digit. Medicine Ping-Hsuan Hsieh, Chin Lin, Chin-Sheng Lin, Wei-Ting Liu, Tsung-Kun Lin, Dung-Jang Tsai, Yi-Jen Hung, Yuan-Hao Chen, Chih-Yuan Lin, Shih-Hua Lin, Chien-Sung Tsai
2025	J	`jnl`	Linearity Analysis of Source-Degenerated Differential Pairs for Wireline Applications. IEEE Open J. Circuits Syst. Kunal Yadav, Ping-Hsuan Hsieh, Anthony Chan Carusone
2025	J	`jnl`	Universal Atrial Fibrillation Screening Using Electrocardiographic Artificial Intelligence: A Cost-Effective Approach in Rural Communities. J. Medical Syst. Wei-Ting Liu, Chin-Sheng Lin, Chin Lin, Tsung-Kun Lin, Wen-Yu Lin, Chiao-Chin Lee, Chiao-Hsiang Chang, Chien-Sung Tsai, Yi-Jen Hung, Ping-Hsuan Hsieh
2024	—	`conf`	7.7 A 2.16pJ/b 112Gb/s PAM-4 Transceiver with Time-Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28nm CMOS. ISSCC Yen-Po Lin, Pen-Jui Peng, Chun-Chang Lu, Po-Ting Shen, Yun-Cheng Jao, Ping-Hsuan Hsieh
2024	—	`conf`	A 39-Gb/s PAM-3 Transmitter and ADC-Based Receiver Chipset in CMOS Technologies. A-SSCC Yen-Po Lin, Chun-Chang Lu, Mei-Hsuan Lu, Yueh-Cheng Tsai, Ping-Hsuan Hsieh, Pen-Jui Peng
2024	—	`conf`	A CMOS Transimpedance Amplifier Accommodating Wide CPD and Input Bias Range for Chaos Lidar. APCCAS Hao-Wei Wu, Chung-Yuan Wang, Huan-Jhong Chen, Yi-Cheng Lin, Ping-Hsuan Hsieh, Fan-Yi Lin, Yuan-Hao Huang, Po-Chiun Huang
2024	—	`conf`	A Switched-Capacitor Cross-Correlation-Based Time-of-Flight Design for Pulsed Chaos Lidar Systems. APCCAS Yung-Han Tseng, Yi-Cheng Lin, Sheng-Che Lin, Ping-Hsuan Hsieh, Cheng-Ting Lee, Chih-Hao Chang, Fan-Yi Lin
2022	J	`jnl`	Introduction to the Special Section on Smart Imaging. IEEE Open J. Circuits Syst. Ping-Hsuan Hsieh, Vanessa Chen
2022	J	`jnl`	Loop Dynamics Analysis of PAM-4 Mueller-Muller Clock and Data Recovery System. IEEE Open J. Circuits Syst. Kunal Yadav, Ping-Hsuan Hsieh, Anthony Chan Carusone
2021	—	`conf`	A Cross-Correlation-Based Time-of-Flight Design for Chaos Lidar Systems. A-SSCC Yi-Cheng Lin, Ping-Hsuan Hsieh, Jian-Lun Hong, Yu-Hsiang Lai, Jun-Da Chen, Fan-Yi Lin, Yuan-Hao Huang, Po-Chiun Huang
2021	—	`conf`	F3: Silicon Technologies in the Fight Against Pandemics - From Point of Care to Computational Epidemiology. ISSCC Nick Van Helleputte, Arijit Raychowdhury, Ping-Hsuan Hsieh, Jun Deguchi, Matteo Perenzoni, Esther Rodríguez-Villegas, Long Yan, Andreia Cathelin, Keith A. Bowman, Chris Van Hoof
2021	J	`jnl`	Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits Friedel Gerfers, Ping-Hsuan Hsieh, Dejan Markovic, Jun Deguchi, Eric Karl
2021	J	`jnl`	Introduction to the Special Section on High-Speed Wireline and Optical Communication Circuits and Systems. IEEE Open J. Circuits Syst. Ping-Hsuan Hsieh, Chun-Ming Hsu, Yunzhi Dong
2021	—	`conf`	Session 29 Overview: Digital Circuits for Computing, Clocking and Power Management DIGITAL CIRCUITS SUBCOMMITTEE. ISSCC Ping-Hsuan Hsieh, Mingoo Seok, Keith A. Bowman
2020	C	`conf`	A 13.56-MHz Wireless Power Transfer Transmitter with Impedance Compression Network for Biomedical Applications. ISCAS Fu-Wen Chang, Ping-Hsuan Hsieh
2020	C	`conf`	A Calibration Technique for P-SSHI-Phi Interface for Piezoelectric Energy Harvesting. ISCAS Yu-Shyang Huang, Hung-Chen Chen, Ping-Hsuan Hsieh, Yi-Chung Shu
2019	C	`conf`	A Digital-to-Time Converter with Coupled Phase-Rotating LC Oscillators in 90-nm CMOS Technology. ISCAS Ming-Ting Wu, Hao-Che Hsu, Ping-Hsuan Hsieh
2019	C	`conf`	Design and Implementation of a Memristor-Based Oscillator. ISCAS Ping-Hsuan Hsieh, Ming-Li Tang, Sheng-Yen Hsu, Meng-Hung Lin, Yi-Hsiu Chen
2018	J	`jnl`	Electromagnetic Energy Harvester Interface Design for Wearable Applications. IEEE Trans. Circuits Syst. II Express Briefs Shih-Wei Wang, Yi-Wen Ke, Po-Chiun Huang, Ping-Hsuan Hsieh
2017	C	`conf`	Integration of energy-recycling logic and wireless power transfer for ultra-low-power implantables. ISCAS Hsin-Tzu Lin, Yi-Chung Wu, Ping-Hsuan Hsieh, Chia-Hsiang Yang
2016	J	`jnl`	A Standard-Cell-Design-Flow Compatible Energy-Recycling Logic With 70% Energy Saving. IEEE Trans. Circuits Syst. I Regul. Pap. Cheng-Yen Lee, Ping-Hsuan Hsieh, Chia-Hsiang Yang
2016	—	`conf`	A series-SSHI-Phi interface circuit for piezoelectric energy harvesting with 163% improvement in extracted power at off-resonance. A-SSCC Chi-Huan Chen, Hung-Chen Chen, Yu-Shyang Huang, Ping-Hsuan Hsieh, Ping-Hsien Wu, Yi-Chung Shu
2016	B	`conf`	IoT: Source of test challenges. ETS Erik Jan Marinissen, Yervant Zorian, Mario Konijnenburg, Chih-Tsun Huang, Ping-Hsuan Hsieh, Peter Cockburn, Jeroen Delvaux, Vladimir Rozic, Bohan Yang, Dave Singelée, Ingrid Verbauwhede, Cedric Mayor, Robert Van Rijsinge, Cocoy Reyes
2015	J	`jnl`	A 0.003 mm IEEE J. Solid State Circuits Jen-Huan Tsai, Hui-Huan Wang, Yang-Chi Yen, Chang-Ming Lai, Yen-Ju Chen, Po-Chiun Huang, Ping-Hsuan Hsieh, Hsin Chen, Chao-Cheng Lee
2015	J	`jnl`	A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology. IEEE J. Solid State Circuits Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman
2015	—	`conf`	A 100-MHz radio-frequency energy harvester for passively powered devices. ECCTD Chih-Hsien Chou, Ping-Hsuan Hsieh
2015	J	`jnl`	An RF Energy Harvester With 44.1% PCE at Input Available Power of -12 dBm. IEEE Trans. Circuits Syst. I Regul. Pap. Ping-Hsuan Hsieh, Chih-Hsien Chou, Tao Chiang
2014	—	`conf`	28.3 A frequency-defined vernier digital-to-time converter for impulse radar systems in 65nm CMOS. ISSCC Yu-Hsien Kao, Chang-Ming Lai, Jen-Ming Wu, Po-Chiun Huang, Ping-Hsuan Hsieh, Ta-Shun Chu
2014	—	`conf`	A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology. CICC Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman
2013	—	`conf`	A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI. ISSCC Yong Liu, Ping-Hsuan Hsieh, Seongwon Kim, Jae-sun Seo, Robert K. Montoye, Leland Chang, José A. Tierno, Daniel J. Friedman
2012	J	`jnl`	A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology. IEEE J. Solid State Circuits John F. Bulzacchelli, Christian Menolfi, Troy J. Beukema, Daniel W. Storaska, Juergen Hertle, David Hanson, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, William R. Kelly, L. R. Chieco, Glenn Ritter, J. A. Sorice, Jon Garlett, Robert Callan, Matthias Braendli, Peter Buchmann, Marcel A. Kossel, Thomas Toifl, Daniel J. Friedman
2012	—	`conf`	A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology. ISSCC John F. Bulzacchelli, Troy J. Beukema, Daniel W. Storaska, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Christian Menolfi, David Hanson, Juergen Hertle, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, William R. Kelly, Glenn Ritter, Jon Garlett, Robert Callan, Thomas Toifl, Daniel J. Friedman
2010	J	`jnl`	A Phase-Selecting Digital Phase-Locked Loop With Bandwidth Tracking in 65-nm CMOS Technology. IEEE J. Solid State Circuits Ping-Hsuan Hsieh, Jay Maxey, Chih-Kong Ken Yang
2009	—	`conf`	A nonlinear phase detector for digital phase locked loops. CICC Ping-Hsuan Hsieh, Jay Maxey, Chih-Kong Ken Yang
2009	J	`jnl`	Minimizing the Supply Sensitivity of a CMOS Ring Oscillator Through Jointly Biasing the Supply and Control Voltages. IEEE J. Solid State Circuits Ping-Hsuan Hsieh, Jay Maxey, Chih-Kong Ken Yang
2008	—	`conf`	Minimizing the supply sensitivity of CMOS ring oscillator by jointly biasing the supply and control voltage. CICC Ping-Hsuan Hsieh, Jay Maxey, Chih-Kong Ken Yang
2007	J	`jnl`	Technique to Reduce the Resolution Requirement of Digitally Controlled Oscillators for Digital PLLs. IEEE Trans. Circuits Syst. II Express Briefs Ping-Hsuan Hsieh, Chih-Kong Ken Yang
2003	—	`conf`	CMOS LC oscillator using variable mean frequency. CICC Ping-Hsuan Hsieh, Jack Judy, Chih-Kong Ken Yang