Pin Su

31 papers A 4C 6Journal 7Unranked 14
YearRankTypeTitle / Venue / Authors
2017 C conf
Exploration and evaluation of low-dropout linear voltage regulator with FinFET, TFET and hybrid TFET-FinFET implementations.
ISCAS
Chia-Ning Chang, Yin-Nien Chen, Po-Tsang Huang, Pin Su, Ching-Te Chuang
2016 A conf
Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells.
ISLPED
Chang-Hung Yu, Pin Su, Ching-Te Chuang
2016 — conf
Exploration and evaluation of hybrid TFET-MOSFET monolithic 3D SRAMs considering interlayer coupling.
ICICDT
Jian-Hao Wang, Yin-Nien Chen, Pin Su, Ching-Te Chuang
2016 C conf
Investigation of BTI reliability for monolithic 3D 6T SRAM with ultra-thin-body GeOI MOSFETs.
ISCAS
Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2015 — conf
Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices.
ICICDT
Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2015 C conf
Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness.
ISCAS
Chien-Ju Chen, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2015 — conf
Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications.
SoCC
Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2015 C conf
Impacts of NBTI and PBTI on ultra-thin-body GeOI 6T SRAM cells.
ISCAS
Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
2015 J jnl
Investigation and comparison of analog figures-of-merit for TFET and FinFET considering work-function variation.
Microelectron. Reliab.
Ko-Chun Lee, Ming-Long Fan, Pin Su
2014 C conf
Evaluation of Read- and Write-Assist circuits for GeOI FinFET 6T SRAM cells.
ISCAS
Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
2014 J jnl
Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2014 J jnl
Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2014 C conf
Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling.
ISCAS
Ming-Long Fan, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang
2014 J jnl
Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits.
Microelectron. Reliab.
Ming-Long Fan, Shao-Yu Yang, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang
2014 A conf
Ultra-low voltage mixed TFET-MOSFET 8T SRAM cell.
ISLPED
Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2013 — conf
Device design and analysis of logic circuits and SRAMs for Germanium FinFETs on SOI and bulk substrates.
ISQED
Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
2013 — conf
Impacts of single trap induced random telegraph noise on Si and Ge nanowire FETs, 6T SRAM cells and logic circuits.
ICICDT
Shao-Yu Yang, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2012 — conf
A comparative analysis of tunneling FET circuit switching characteristics and SRAM stability and performance.
ESSDERC
Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Ming-Fu Tsai, Chia-Hao Pao, Pin Su, Ching-Te Chuang
2012 — conf
A comprehensive comparative analysis of FinFET and Trigate device, SRAM and logic circuits.
APCCAS
Chia-Hao Pao, Ming-Long Fan, Ming-Fu Tsai, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2012 — conf
Impacts of random telegraph noise on the analog properties of FinFET and trigate devices and Widlar current source.
ICICDT
Chia-Hao Pao, Ming-Long Fan, Ming-Fu Tsai, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2012 J jnl
Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs.
IEEE Trans. Very Large Scale Integr. Syst.
Chien-Yu Hsieh, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2012 — conf
Stability and performance optimization of InGaAs-OI and GeOI hetero-channel SRAM cells.
ESSDERC
Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
2012 J jnl
Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Ming-Long Fan, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang
2012 — conf
Variation tolerant CLSAs for nanoscale Bulk-CMOS and FinFET SRAM.
APCCAS
Ming-Fu Tsai, Jen-Huan Tsai, Ming-Long Fan, Pin Su, Ching-Te Chuang
2011 J jnl
Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
2011 A conf
Analysis of power-performance for ultra-thin-body GeOI logic circuits.
ISLPED
Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
2009 A conf
Design and analysis of ultra-thin-body SOI based subthreshold SRAM.
ISLPED
Vita Pi-Ho Hu, Yu-Sheng Wu, Ming-Long Fan, Pin Su, Ching-Te Chuang
2003 — conf
A unified model for partial-depletion and full-depletion SOI circuit designs: using BSIMPD as a foundation.
CICC
Pin Su, Samel K. H. Fung, Peter W. Wyatt, Hui Wan, Mansun Chan, Ali M. Niknejad, Chenming Hu
2002 — conf
Studying the Impact of Gate Tunneling on Dynamic Behaviors of Partially-Depleted SOI CMOS Using BSIMPD.
ISQED
Pin Su, Samel K. H. Fung, Weidong Liu, Chenming Hu
2001 — conf
Methodology of self-heating free parameter extraction and circuit simulation for SOI CMOS.
CICC
Hajime Nakayama, Pin Su, Chenming Hu, Motoaki Nakamura, Hiroshi Komatsu, Kaneyoshi Takeshita, Yasutoshi Komatsu
2000 — conf
BSIMPD: a partial-depletion SOI MOSFET model for deep-submicron CMOS designs.
CICC
Pin Su, Samuel K. H. Fung, Stephen Tang, Fariborz Assaderaghi, Chenming Hu